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Merge branch 'main' into vector-step-int-range
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clang/docs/ShadowCallStack.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ The instrumentation makes use of the platform register ``x18`` on AArch64,
6161
``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with
6262
hardware shadow stack, which needs `Zicfiss`_ and ``-fcf-protection=return``.
6363
Users can choose between the software and hardware based shadow stack
64-
implementation on RISC-V backend by passing ``-fsanitize=shadowcallstack``
64+
implementation on RISC-V backend by passing ``-fsanitize=shadow-call-stack``
6565
or ``Zicfiss`` with ``-fcf-protection=return``.
6666
For simplicity we will refer to this as the ``SCSReg``. On some platforms,
6767
``SCSReg`` is reserved, and on others, it is designated as a scratch register.

clang/include/clang/CIR/MissingFeatures.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,7 @@ struct MissingFeatures {
217217
static bool intrinsics() { return false; }
218218
static bool isMemcpyEquivalentSpecialMember() { return false; }
219219
static bool isTrivialCtorOrDtor() { return false; }
220+
static bool lambdaCaptures() { return false; }
220221
static bool lambdaFieldToName() { return false; }
221222
static bool loopInfoStack() { return false; }
222223
static bool lowerAggregateLoadStore() { return false; }

clang/lib/CIR/CodeGen/CIRGenDecl.cpp

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -520,7 +520,7 @@ void CIRGenFunction::emitExprAsInit(const Expr *init, const ValueDecl *d,
520520
llvm_unreachable("bad evaluation kind");
521521
}
522522

523-
void CIRGenFunction::emitDecl(const Decl &d) {
523+
void CIRGenFunction::emitDecl(const Decl &d, bool evaluateConditionDecl) {
524524
switch (d.getKind()) {
525525
case Decl::BuiltinTemplate:
526526
case Decl::TranslationUnit:
@@ -608,11 +608,14 @@ void CIRGenFunction::emitDecl(const Decl &d) {
608608
case Decl::UsingDirective: // using namespace X; [C++]
609609
assert(!cir::MissingFeatures::generateDebugInfo());
610610
return;
611-
case Decl::Var: {
611+
case Decl::Var:
612+
case Decl::Decomposition: {
612613
const VarDecl &vd = cast<VarDecl>(d);
613614
assert(vd.isLocalVarDecl() &&
614615
"Should not see file-scope variables inside a function!");
615616
emitVarDecl(vd);
617+
if (evaluateConditionDecl)
618+
maybeEmitDeferredVarDeclInit(&vd);
616619
return;
617620
}
618621
case Decl::OpenACCDeclare:
@@ -632,7 +635,6 @@ void CIRGenFunction::emitDecl(const Decl &d) {
632635
case Decl::ImplicitConceptSpecialization:
633636
case Decl::TopLevelStmt:
634637
case Decl::UsingPack:
635-
case Decl::Decomposition: // This could be moved to join Decl::Var
636638
case Decl::OMPDeclareReduction:
637639
case Decl::OMPDeclareMapper:
638640
cgm.errorNYI(d.getSourceRange(),
@@ -797,3 +799,11 @@ void CIRGenFunction::emitAutoVarTypeCleanup(
797799
assert(!cir::MissingFeatures::ehCleanupFlags());
798800
ehStack.pushCleanup<DestroyObject>(cleanupKind, addr, type, destroyer);
799801
}
802+
803+
void CIRGenFunction::maybeEmitDeferredVarDeclInit(const VarDecl *vd) {
804+
if (auto *dd = dyn_cast_if_present<DecompositionDecl>(vd)) {
805+
for (auto *b : dd->flat_bindings())
806+
if (auto *hd = b->getHoldingVar())
807+
emitVarDecl(*hd);
808+
}
809+
}

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -584,6 +584,15 @@ LValue CIRGenFunction::emitDeclRefLValue(const DeclRefExpr *e) {
584584
return lv;
585585
}
586586

587+
if (const auto *bd = dyn_cast<BindingDecl>(nd)) {
588+
if (e->refersToEnclosingVariableOrCapture()) {
589+
assert(!cir::MissingFeatures::lambdaCaptures());
590+
cgm.errorNYI(e->getSourceRange(), "emitDeclRefLValue: lambda captures");
591+
return LValue();
592+
}
593+
return emitLValue(bd->getBinding());
594+
}
595+
587596
cgm.errorNYI(e->getSourceRange(), "emitDeclRefLValue: unhandled decl type");
588597
return LValue();
589598
}

clang/lib/CIR/CodeGen/CIRGenFunction.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -943,6 +943,7 @@ void CIRGenFunction::emitVariablyModifiedType(QualType type) {
943943
case Type::HLSLInlineSpirv:
944944
case Type::PredefinedSugar:
945945
cgm.errorNYI("CIRGenFunction::emitVariablyModifiedType");
946+
break;
946947

947948
#define TYPE(Class, Base)
948949
#define ABSTRACT_TYPE(Class, Base)

clang/lib/CIR/CodeGen/CIRGenFunction.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -870,6 +870,8 @@ class CIRGenFunction : public CIRGenTypeCache {
870870
void emitAutoVarTypeCleanup(const AutoVarEmission &emission,
871871
clang::QualType::DestructionKind dtorKind);
872872

873+
void maybeEmitDeferredVarDeclInit(const VarDecl *vd);
874+
873875
void emitBaseInitializer(mlir::Location loc, const CXXRecordDecl *classDecl,
874876
CXXCtorInitializer *baseInit);
875877

@@ -1059,7 +1061,7 @@ class CIRGenFunction : public CIRGenTypeCache {
10591061

10601062
void emitCompoundStmtWithoutScope(const clang::CompoundStmt &s);
10611063

1062-
void emitDecl(const clang::Decl &d);
1064+
void emitDecl(const clang::Decl &d, bool evaluateConditionDecl = false);
10631065
mlir::LogicalResult emitDeclStmt(const clang::DeclStmt &s);
10641066
LValue emitDeclRefLValue(const clang::DeclRefExpr *e);
10651067

clang/lib/CIR/CodeGen/CIRGenModule.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1308,8 +1308,13 @@ void CIRGenModule::emitTopLevelDecl(Decl *decl) {
13081308
break;
13091309
}
13101310

1311-
case Decl::Var: {
1311+
case Decl::Var:
1312+
case Decl::Decomposition: {
13121313
auto *vd = cast<VarDecl>(decl);
1314+
if (isa<DecompositionDecl>(decl)) {
1315+
errorNYI(decl->getSourceRange(), "global variable decompositions");
1316+
break;
1317+
}
13131318
emitGlobal(vd);
13141319
break;
13151320
}

clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp

Lines changed: 101 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,9 @@ struct CIRRecordLowering final {
9191
return astContext.getTargetInfo().getABI().starts_with("aapcs");
9292
}
9393

94+
/// Helper function to check if the target machine is BigEndian.
95+
bool isBigEndian() const { return astContext.getTargetInfo().isBigEndian(); }
96+
9497
CharUnits bitsToCharUnits(uint64_t bitOffset) {
9598
return astContext.toCharUnitsFromBits(bitOffset);
9699
}
@@ -771,7 +774,104 @@ void CIRRecordLowering::computeVolatileBitfields() {
771774
!cirGenTypes.getCGModule().getCodeGenOpts().AAPCSBitfieldWidth)
772775
return;
773776

774-
assert(!cir::MissingFeatures::armComputeVolatileBitfields());
777+
for (auto &[field, info] : bitFields) {
778+
mlir::Type resLTy = cirGenTypes.convertTypeForMem(field->getType());
779+
780+
if (astContext.toBits(astRecordLayout.getAlignment()) <
781+
getSizeInBits(resLTy).getQuantity())
782+
continue;
783+
784+
// CIRRecordLowering::setBitFieldInfo() pre-adjusts the bit-field offsets
785+
// for big-endian targets, but it assumes a container of width
786+
// info.storageSize. Since AAPCS uses a different container size (width
787+
// of the type), we first undo that calculation here and redo it once
788+
// the bit-field offset within the new container is calculated.
789+
const unsigned oldOffset =
790+
isBigEndian() ? info.storageSize - (info.offset + info.size)
791+
: info.offset;
792+
// Offset to the bit-field from the beginning of the struct.
793+
const unsigned absoluteOffset =
794+
astContext.toBits(info.storageOffset) + oldOffset;
795+
796+
// Container size is the width of the bit-field type.
797+
const unsigned storageSize = getSizeInBits(resLTy).getQuantity();
798+
// Nothing to do if the access uses the desired
799+
// container width and is naturally aligned.
800+
if (info.storageSize == storageSize && (oldOffset % storageSize == 0))
801+
continue;
802+
803+
// Offset within the container.
804+
unsigned offset = absoluteOffset & (storageSize - 1);
805+
// Bail out if an aligned load of the container cannot cover the entire
806+
// bit-field. This can happen for example, if the bit-field is part of a
807+
// packed struct. AAPCS does not define access rules for such cases, we let
808+
// clang to follow its own rules.
809+
if (offset + info.size > storageSize)
810+
continue;
811+
812+
// Re-adjust offsets for big-endian targets.
813+
if (isBigEndian())
814+
offset = storageSize - (offset + info.size);
815+
816+
const CharUnits storageOffset =
817+
astContext.toCharUnitsFromBits(absoluteOffset & ~(storageSize - 1));
818+
const CharUnits end = storageOffset +
819+
astContext.toCharUnitsFromBits(storageSize) -
820+
CharUnits::One();
821+
822+
const ASTRecordLayout &layout =
823+
astContext.getASTRecordLayout(field->getParent());
824+
// If we access outside memory outside the record, than bail out.
825+
const CharUnits recordSize = layout.getSize();
826+
if (end >= recordSize)
827+
continue;
828+
829+
// Bail out if performing this load would access non-bit-fields members.
830+
bool conflict = false;
831+
for (const auto *f : recordDecl->fields()) {
832+
// Allow sized bit-fields overlaps.
833+
if (f->isBitField() && !f->isZeroLengthBitField())
834+
continue;
835+
836+
const CharUnits fOffset = astContext.toCharUnitsFromBits(
837+
layout.getFieldOffset(f->getFieldIndex()));
838+
839+
// As C11 defines, a zero sized bit-field defines a barrier, so
840+
// fields after and before it should be race condition free.
841+
// The AAPCS acknowledges it and imposes no restritions when the
842+
// natural container overlaps a zero-length bit-field.
843+
if (f->isZeroLengthBitField()) {
844+
if (end > fOffset && storageOffset < fOffset) {
845+
conflict = true;
846+
break;
847+
}
848+
}
849+
850+
const CharUnits fEnd =
851+
fOffset +
852+
astContext.toCharUnitsFromBits(astContext.toBits(
853+
getSizeInBits(cirGenTypes.convertTypeForMem(f->getType())))) -
854+
CharUnits::One();
855+
// If no overlap, continue.
856+
if (end < fOffset || fEnd < storageOffset)
857+
continue;
858+
859+
// The desired load overlaps a non-bit-field member, bail out.
860+
conflict = true;
861+
break;
862+
}
863+
864+
if (conflict)
865+
continue;
866+
// Write the new bit-field access parameters.
867+
// As the storage offset now is defined as the number of elements from the
868+
// start of the structure, we should divide the Offset by the element size.
869+
info.volatileStorageOffset =
870+
storageOffset /
871+
astContext.toCharUnitsFromBits(storageSize).getQuantity();
872+
info.volatileStorageSize = storageSize;
873+
info.volatileOffset = offset;
874+
}
775875
}
776876

777877
void CIRRecordLowering::accumulateBases(const CXXRecordDecl *cxxRecordDecl) {

clang/lib/CIR/CodeGen/CIRGenStmt.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -363,8 +363,8 @@ mlir::LogicalResult CIRGenFunction::emitIfStmt(const IfStmt &s) {
363363
mlir::LogicalResult CIRGenFunction::emitDeclStmt(const DeclStmt &s) {
364364
assert(builder.getInsertionBlock() && "expected valid insertion point");
365365

366-
for (const Decl *I : s.decls())
367-
emitDecl(*I);
366+
for (const Decl *i : s.decls())
367+
emitDecl(*i, /*evaluateConditionDecl=*/true);
368368

369369
return mlir::success();
370370
}
@@ -875,7 +875,7 @@ mlir::LogicalResult CIRGenFunction::emitSwitchStmt(const clang::SwitchStmt &s) {
875875
return mlir::failure();
876876

877877
if (s.getConditionVariable())
878-
emitDecl(*s.getConditionVariable());
878+
emitDecl(*s.getConditionVariable(), /*evaluateConditionDecl=*/true);
879879

880880
mlir::Value condV = emitScalarExpr(s.getCond());
881881

clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
namespace hlsl {
1313
namespace __detail {
1414

15-
constexpr vector<uint, 4> d3d_color_to_ubyte4_impl(vector<float, 4> V) {
15+
constexpr int4 d3d_color_to_ubyte4_impl(float4 V) {
1616
// Use the same scaling factor used by FXC, and DXC for DXIL
1717
// (i.e., 255.001953)
1818
// https://github.com/microsoft/DirectXShaderCompiler/blob/070d0d5a2beacef9eeb51037a9b04665716fd6f3/lib/HLSL/HLOperationLower.cpp#L666C1-L697C2

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