Address comments, includes fix for using wrong signedness

Fix wrong signedness in promotion function.
Make expand code depend on node signedness not on operand extend.

Author: JamesChesterman

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

@@ -2892,8 +2892,13 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
 
 SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
   SmallVector<SDValue, 1> NewOps(N->ops());
-  NewOps[1] = GetPromotedInteger(N->getOperand(1));
-  NewOps[2] = GetPromotedInteger(N->getOperand(2));
+  if (N->getOpcode() == ISD::PARTIAL_REDUCE_SMLA) {
+    NewOps[1] = SExtPromotedInteger(N->getOperand(1));
+    NewOps[2] = SExtPromotedInteger(N->getOperand(2));
+  } else {
+    NewOps[1] = ZExtPromotedInteger(N->getOperand(1));
+    NewOps[2] = ZExtPromotedInteger(N->getOperand(2));
+  }
   return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
 }
 

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -11901,8 +11901,9 @@ SDValue TargetLowering::expandPartialReduceMLA(SDNode *N,
   EVT FullTy = MulLHS.getValueType();
 
   auto ExtendToAccEltVT = [&](SDValue V) {
-    unsigned ExtOpc = V->getOpcode() == ISD::SIGN_EXTEND ? ISD::SIGN_EXTEND
-                                                         : ISD::ZERO_EXTEND;
+    unsigned ExtOpc = V->getOpcode() == ISD::PARTIAL_REDUCE_SMLA
+                          ? ISD::SIGN_EXTEND
+                          : ISD::ZERO_EXTEND;
     EVT ExtVT = V.getValueType().changeVectorElementType(
         Acc.getValueType().getVectorElementType());
     if (ExtVT != FullTy)