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WIP attempt to avoid MCRegAliasIterator
1 parent 5af79ab commit 5e30be8

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4 files changed

+91
-78
lines changed

4 files changed

+91
-78
lines changed

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 30 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2245,25 +2245,43 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
22452245
return true;
22462246
}
22472247

2248-
static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
2249-
const TargetRegisterInfo *TRI) {
2250-
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
2251-
if (MBB.isLiveIn(*R)) {
2252-
return true;
2253-
}
2254-
}
2255-
return false;
2256-
}
2257-
22582248
bool SIFrameLowering::spillCalleeSavedRegisters(
22592249
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
22602250
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
22612251
MachineFunction *MF = MBB.getParent();
22622252
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
22632253
const SIInstrInfo *TII = ST.getInstrInfo();
22642254
const SIRegisterInfo *SITRI = static_cast<const SIRegisterInfo *>(TRI);
2255+
const MachineRegisterInfo &MRI = MF->getRegInfo();
22652256

22662257
if (!ST.useVGPRBlockOpsForCSR()) {
2258+
SparseBitVector<> LiveInRoots;
2259+
if (MRI.tracksLiveness()) {
2260+
for (const auto &LI : MBB.liveins()) {
2261+
for (MCRegUnitMaskIterator MI(LI.PhysReg, TRI); MI.isValid(); ++MI) {
2262+
auto [Unit, UnitLaneMask] = *MI;
2263+
if ((LI.LaneMask & UnitLaneMask).none())
2264+
continue;
2265+
for (MCRegUnitRootIterator RI(Unit, TRI); RI.isValid(); ++RI)
2266+
LiveInRoots.set(*RI);
2267+
}
2268+
}
2269+
}
2270+
2271+
auto UpdateLiveInCheckCanKill = [&](MCRegister Reg) {
2272+
if (!MRI.tracksLiveness())
2273+
return false;
2274+
for (MCRegUnitIterator UI(Reg, TRI); UI.isValid(); ++UI) {
2275+
for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
2276+
if (LiveInRoots.test(*RI))
2277+
return false;
2278+
}
2279+
}
2280+
// Reg is live in to the spill
2281+
MBB.addLiveIn(Reg);
2282+
return true;
2283+
};
2284+
22672285
for (const CalleeSavedInfo &CS : CSI) {
22682286
// Insert the spill to the stack frame.
22692287
unsigned Reg = CS.getReg();
@@ -2279,9 +2297,8 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
22792297
// the incoming register value, so don't kill at the spill point. This
22802298
// happens since we pass some special inputs (workgroup IDs) in the
22812299
// callee saved range.
2282-
const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI);
2283-
TII->storeRegToStackSlotCFI(MBB, MI, Reg, !IsLiveIn, CS.getFrameIdx(),
2284-
RC, TRI);
2300+
TII->storeRegToStackSlotCFI(MBB, MI, Reg, UpdateLiveInCheckCanKill(Reg),
2301+
CS.getFrameIdx(), RC, TRI);
22852302
}
22862303
}
22872304
return true;

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