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[AArch64] Add test coverage for some aba/abal cases (NFC)
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‎llvm/test/CodeGen/AArch64/neon-saba.ll‎

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@@ -174,6 +174,268 @@ define <8 x i8> @saba_sabd_8b(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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ret <8 x i8> %add
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}
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; SABA from ADD(SABD(X, ZEROS))
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define <4 x i32> @saba_sabd_zeros_4s(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_4s:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.4s, v1.4s
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; CHECK-SD-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_4s:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.4s, v1.4s, v2.4s
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; CHECK-GI-NEXT: ret
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%sabd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %b, <4 x i32> zeroinitializer)
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%add = add <4 x i32> %sabd, %a
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ret <4 x i32> %add
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}
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define <2 x i32> @saba_sabd_zeros_2s(<2 x i32> %a, <2 x i32> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_2s:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.2s, v1.2s
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; CHECK-SD-NEXT: add v0.2s, v1.2s, v0.2s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_2s:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.2s, v1.2s, v2.2s
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; CHECK-GI-NEXT: ret
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%sabd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> zeroinitializer)
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%add = add <2 x i32> %sabd, %a
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ret <2 x i32> %add
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}
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define <8 x i16> @saba_sabd_zeros_8h(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_8h:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.8h, v1.8h
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; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_8h:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.8h, v1.8h, v2.8h
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; CHECK-GI-NEXT: ret
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%sabd = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %b, <8 x i16> zeroinitializer)
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%add = add <8 x i16> %sabd, %a
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ret <8 x i16> %add
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}
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define <4 x i16> @saba_sabd_zeros_4h(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_4h:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.4h, v1.4h
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; CHECK-SD-NEXT: add v0.4h, v1.4h, v0.4h
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_4h:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.4h, v1.4h, v2.4h
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; CHECK-GI-NEXT: ret
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%sabd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> zeroinitializer)
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%add = add <4 x i16> %sabd, %a
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ret <4 x i16> %add
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}
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define <16 x i8> @saba_sabd_zeros_16b(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_16b:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.16b, v1.16b
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; CHECK-SD-NEXT: add v0.16b, v1.16b, v0.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_16b:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.16b, v1.16b, v2.16b
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; CHECK-GI-NEXT: ret
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%sabd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %b, <16 x i8> zeroinitializer)
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%add = add <16 x i8> %sabd, %a
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ret <16 x i8> %add
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}
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define <8 x i8> @saba_sabd_zeros_8b(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-SD-LABEL: saba_sabd_zeros_8b:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.8b, v1.8b
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; CHECK-SD-NEXT: add v0.8b, v1.8b, v0.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: saba_sabd_zeros_8b:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: saba v0.8b, v1.8b, v2.8b
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; CHECK-GI-NEXT: ret
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%sabd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> zeroinitializer)
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%add = add <8 x i8> %sabd, %a
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ret <8 x i8> %add
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}
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define <4 x i32> @saba_abs_zeros_4s(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %b, i1 true)
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%add = add <4 x i32> %a, %abs
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ret <4 x i32> %add
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}
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define <2 x i32> @saba_abs_zeros_2s(<2 x i32> %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.2s, v1.2s
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; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %b, i1 true)
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%add = add <2 x i32> %a, %abs
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ret <2 x i32> %add
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}
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define <8 x i16> @saba_abs_zeros_8h(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.8h, v1.8h
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; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %b, i1 true)
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%add = add <8 x i16> %a, %abs
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ret <8 x i16> %add
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}
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define <4 x i16> @saba_abs_zeros_4h(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.4h, v1.4h
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; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %b, i1 true)
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%add = add <4 x i16> %a, %abs
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ret <4 x i16> %add
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}
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define <16 x i8> @saba_abs_zeros_16b(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.16b, v1.16b
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; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %b, i1 true)
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%add = add <16 x i8> %a, %abs
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ret <16 x i8> %add
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}
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define <8 x i8> @saba_abs_zeros_8b(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: saba_abs_zeros_8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.8b, v1.8b
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; CHECK-NEXT: add v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%abs = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %b, i1 true)
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%add = add <8 x i8> %a, %abs
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ret <8 x i8> %add
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}
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; SABAL from ADD(ZEXT(SABD(X, ZEROS)))
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define <2 x i64> @sabal_sabd_zeros_2s(<2 x i64> %a, <2 x i32> %b) #0 {
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; CHECK-SD-LABEL: sabal_sabd_zeros_2s:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.2s, v1.2s
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; CHECK-SD-NEXT: uaddw v0.2d, v0.2d, v1.2s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sabal_sabd_zeros_2s:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: sabal v0.2d, v1.2s, v2.2s
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; CHECK-GI-NEXT: ret
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%sabd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> zeroinitializer)
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%sabd.zext = zext <2 x i32> %sabd to <2 x i64>
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%add = add <2 x i64> %sabd.zext, %a
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ret <2 x i64> %add
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}
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define <4 x i32> @sabal_sabd_zeros_4h(<4 x i32> %a, <4 x i16> %b) #0 {
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; CHECK-SD-LABEL: sabal_sabd_zeros_4h:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.4h, v1.4h
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; CHECK-SD-NEXT: uaddw v0.4s, v0.4s, v1.4h
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sabal_sabd_zeros_4h:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: sabal v0.4s, v1.4h, v2.4h
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; CHECK-GI-NEXT: ret
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%sabd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> zeroinitializer)
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%sabd.zext = zext <4 x i16> %sabd to <4 x i32>
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%add = add <4 x i32> %sabd.zext, %a
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ret <4 x i32> %add
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}
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define <8 x i16> @sabal_sabd_zeros_8b(<8 x i16> %a, <8 x i8> %b) #0 {
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; CHECK-SD-LABEL: sabal_sabd_zeros_8b:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: abs v1.8b, v1.8b
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; CHECK-SD-NEXT: uaddw v0.8h, v0.8h, v1.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sabal_sabd_zeros_8b:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
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; CHECK-GI-NEXT: sabal v0.8h, v1.8b, v2.8b
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; CHECK-GI-NEXT: ret
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%sabd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> zeroinitializer)
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%sabd.zext = zext <8 x i8> %sabd to <8 x i16>
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%add = add <8 x i16> %sabd.zext, %a
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ret <8 x i16> %add
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}
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define <2 x i64> @sabal_abs_zeros_2s(<2 x i64> %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: sabal_abs_zeros_2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.2s, v1.2s
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; CHECK-NEXT: uaddw v0.2d, v0.2d, v1.2s
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; CHECK-NEXT: ret
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%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %b, i1 true)
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%abs.zext = zext <2 x i32> %abs to <2 x i64>
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%add = add <2 x i64> %a, %abs.zext
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ret <2 x i64> %add
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}
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define <4 x i32> @sabal_abs_zeros_4h(<4 x i32> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: sabal_abs_zeros_4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.4h, v1.4h
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; CHECK-NEXT: uaddw v0.4s, v0.4s, v1.4h
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; CHECK-NEXT: ret
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%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %b, i1 true)
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%abs.zext = zext <4 x i16> %abs to <4 x i32>
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%add = add <4 x i32> %a, %abs.zext
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ret <4 x i32> %add
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}
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define <8 x i16> @sabal_abs_zeros_8b(<8 x i16> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: sabal_abs_zeros_8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: abs v1.8b, v1.8b
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; CHECK-NEXT: uaddw v0.8h, v0.8h, v1.8b
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; CHECK-NEXT: ret
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%abs = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %b, i1 true)
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%abs.zext = zext <8 x i8> %abs to <8 x i16>
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%add = add <8 x i16> %a, %abs.zext
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ret <8 x i16> %add
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}
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
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declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)

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