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[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444)
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24 files changed

+46
-39
lines changed

24 files changed

+46
-39
lines changed

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515

1616
namespace llvm {
1717

18+
class MCRegister;
1819
class raw_ostream;
1920

2021
/// MCParsedAsmOperand - This abstract class represents a source-level assembly
@@ -57,7 +58,7 @@ class MCParsedAsmOperand {
5758
virtual bool isImm() const = 0;
5859
/// isReg - Is this a register operand?
5960
virtual bool isReg() const = 0;
60-
virtual unsigned getReg() const = 0;
61+
virtual MCRegister getReg() const = 0;
6162

6263
/// isMem - Is this a memory operand?
6364
virtual bool isMem() const = 0;

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -514,9 +514,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
514514
/// by the tied-operands checks in the AsmMatcher. This method can be
515515
/// overridden to allow e.g. a sub- or super-register as the tied operand.
516516
virtual bool areEqualRegs(const MCParsedAsmOperand &Op1,
517-
const MCParsedAsmOperand &Op2) const {
518-
return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg();
519-
}
517+
const MCParsedAsmOperand &Op2) const;
520518

521519
// Return whether this parser uses assignment statements with equals tokens
522520
virtual bool equalIsAsmAssignment() { return true; };

llvm/lib/MC/MCParser/MCTargetAsmParser.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
1010
#include "llvm/MC/MCContext.h"
11+
#include "llvm/MC/MCRegister.h"
1112

1213
using namespace llvm;
1314

@@ -48,3 +49,8 @@ ParseStatus MCTargetAsmParser::parseDirective(AsmToken DirectiveID) {
4849
return ParseStatus::Failure;
4950
return ParseStatus::NoMatch;
5051
}
52+
53+
bool MCTargetAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
54+
const MCParsedAsmOperand &Op2) const {
55+
return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg();
56+
}

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,7 @@ class AArch64Operand : public MCParsedAsmOperand {
654654
return Barrier.HasnXSModifier;
655655
}
656656

657-
unsigned getReg() const override {
657+
MCRegister getReg() const override {
658658
assert(Kind == k_Register && "Invalid access!");
659659
return Reg.RegNum;
660660
}

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -981,7 +981,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
981981
return Imm.Type;
982982
}
983983

984-
unsigned getReg() const override {
984+
MCRegister getReg() const override {
985985
assert(isRegKind());
986986
return Reg.RegNo;
987987
}

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1002,7 +1002,7 @@ class ARMOperand : public MCParsedAsmOperand {
10021002
return StringRef(Tok.Data, Tok.Length);
10031003
}
10041004

1005-
unsigned getReg() const override {
1005+
MCRegister getReg() const override {
10061006
assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
10071007
return Reg.RegNum;
10081008
}

llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ class AVROperand : public MCParsedAsmOperand {
195195
return Tok;
196196
}
197197

198-
unsigned getReg() const override {
198+
MCRegister getReg() const override {
199199
assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
200200

201201
return RegImm.Reg;

llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ struct BPFOperand : public MCParsedAsmOperand {
148148
/// getEndLoc - Gets location of the last token of this operand
149149
SMLoc getEndLoc() const override { return EndLoc; }
150150

151-
unsigned getReg() const override {
151+
MCRegister getReg() const override {
152152
assert(Kind == Register && "Invalid type access!");
153153
return Reg.RegNum;
154154
}

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,7 @@ struct CSKYOperand : public MCParsedAsmOperand {
400400
/// Gets location of the last token of this operand.
401401
SMLoc getEndLoc() const override { return EndLoc; }
402402

403-
unsigned getReg() const override {
403+
MCRegister getReg() const override {
404404
assert(Kind == Register && "Invalid type access!");
405405
return Reg.RegNum;
406406
}

llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ struct HexagonOperand : public MCParsedAsmOperand {
245245
/// getEndLoc - Get the location of the last token of this operand.
246246
SMLoc getEndLoc() const override { return EndLoc; }
247247

248-
unsigned getReg() const override {
248+
MCRegister getReg() const override {
249249
assert(Kind == Register && "Invalid access!");
250250
return Reg.RegNum;
251251
}

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