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amilendraamilendra
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[CLANG][AArch64] Add mfloat8_t support for more SVE load intrinsics (#145383)
Add mfloat8_t support for the following SVE load intrinsics. - SVLD1RO - SVLD1RQ - SVLDFF1 - SVLDFF1_VNUM - SVLDNF1 - SVLDNF1_VNUM
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‎clang/include/clang/Basic/arm_sve.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ def SVLD1UW_GATHER_INDEX_S : MInst<"svld1uw_gather[_{2}base]_index_{d}", "dPul
121121

122122

123123
// First-faulting load one vector (scalar base)
124-
def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">;
124+
def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">;
125125
def SVLDFF1SB : MInst<"svldff1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldff1">;
126126
def SVLDFF1UB : MInst<"svldff1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1">;
127127
def SVLDFF1SH : MInst<"svldff1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldff1">;
@@ -130,7 +130,7 @@ def SVLDFF1SW : MInst<"svldff1sw_{d}", "dPU", "lUl", [IsLoad],
130130
def SVLDFF1UW : MInst<"svldff1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1">;
131131

132132
// First-faulting load one vector (scalar base, VL displacement)
133-
def SVLDFF1_VNUM : MInst<"svldff1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">;
133+
def SVLDFF1_VNUM : MInst<"svldff1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">;
134134
def SVLDFF1SB_VNUM : MInst<"svldff1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldff1">;
135135
def SVLDFF1UB_VNUM : MInst<"svldff1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1">;
136136
def SVLDFF1SH_VNUM : MInst<"svldff1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldff1">;
@@ -223,7 +223,7 @@ def SVLDFF1SW_GATHER_INDEX_S : MInst<"svldff1sw_gather[_{2}base]_index_{d}", "dP
223223
def SVLDFF1UW_GATHER_INDEX_S : MInst<"svldff1uw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">;
224224

225225
// Non-faulting load one vector (scalar base)
226-
def SVLDNF1 : MInst<"svldnf1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">;
226+
def SVLDNF1 : MInst<"svldnf1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">;
227227
def SVLDNF1SB : MInst<"svldnf1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldnf1">;
228228
def SVLDNF1UB : MInst<"svldnf1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnf1">;
229229
def SVLDNF1SH : MInst<"svldnf1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldnf1">;
@@ -232,7 +232,7 @@ def SVLDNF1SW : MInst<"svldnf1sw_{d}", "dPU", "lUl", [IsLoad],
232232
def SVLDNF1UW : MInst<"svldnf1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnf1">;
233233

234234
// Non-faulting load one vector (scalar base, VL displacement)
235-
def SVLDNF1_VNUM : MInst<"svldnf1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">;
235+
def SVLDNF1_VNUM : MInst<"svldnf1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">;
236236
def SVLDNF1SB_VNUM : MInst<"svldnf1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldnf1">;
237237
def SVLDNF1UB_VNUM : MInst<"svldnf1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnf1">;
238238
def SVLDNF1SH_VNUM : MInst<"svldnf1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldnf1">;
@@ -258,7 +258,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
258258
}
259259

260260
// Load one quadword and replicate (scalar base)
261-
def SVLD1RQ : SInst<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
261+
def SVLD1RQ : SInst<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfdm", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
262262

263263
let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
264264
def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc", "b", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
@@ -283,7 +283,7 @@ defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", "aarch64_sve_ld4_sret">
283283

284284
// Load one octoword and replicate (scalar base)
285285
let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in {
286-
def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1ro">;
286+
def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfdm", MergeNone, "aarch64_sve_ld1ro">;
287287
}
288288
let SVETargetGuard = "sve,f64mm,bf16", SMETargetGuard = InvalidMode in {
289289
def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, "aarch64_sve_ld1ro">;

‎clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
44
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
55
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
6+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
67

78
// REQUIRES: aarch64-registered-target
89

@@ -15,6 +16,20 @@
1516
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
1617
#endif
1718

19+
// CHECK-LABEL: @test_svld1ro_mf8(
20+
// CHECK-NEXT: entry:
21+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
22+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
23+
//
24+
// CPP-CHECK-LABEL: @_Z16test_svld1ro_mf8u10__SVBool_tPKu6__mfp8(
25+
// CPP-CHECK-NEXT: entry:
26+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
27+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
28+
//
29+
svmfloat8_t test_svld1ro_mf8(svbool_t pg, mfloat8_t const *base) {
30+
return SVE_ACLE_FUNC(svld1ro, _mf8, , )(pg, base);
31+
}
32+
1833
// CHECK-LABEL: @test_svld1ro_s8(
1934
// CHECK-NEXT: entry:
2035
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])

‎clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,21 @@
2323
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
2424
#endif
2525

26+
// CHECK-LABEL: @test_svld1rq_mf8(
27+
// CHECK-NEXT: entry:
28+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
29+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
30+
//
31+
// CPP-CHECK-LABEL: @_Z16test_svld1rq_mf8u10__SVBool_tPKu6__mfp8(
32+
// CPP-CHECK-NEXT: entry:
33+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
34+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
35+
//
36+
svmfloat8_t test_svld1rq_mf8(svbool_t pg, mfloat8_t const *base) MODE_ATTR
37+
{
38+
return SVE_ACLE_FUNC(svld1rq,_mf8,,)(pg, base);
39+
}
40+
2641
// CHECK-LABEL: @test_svld1rq_s8(
2742
// CHECK-NEXT: entry:
2843
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])

‎clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,21 @@
1414
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
1515
#endif
1616

17+
// CHECK-LABEL: @test_svldff1_mf8(
18+
// CHECK-NEXT: entry:
19+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
20+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
21+
//
22+
// CPP-CHECK-LABEL: @_Z16test_svldff1_mf8u10__SVBool_tPKu6__mfp8(
23+
// CPP-CHECK-NEXT: entry:
24+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
25+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
26+
//
27+
svmfloat8_t test_svldff1_mf8(svbool_t pg, const mfloat8_t *base)
28+
{
29+
return SVE_ACLE_FUNC(svldff1,_mf8,,)(pg, base);
30+
}
31+
1732
// CHECK-LABEL: @test_svldff1_s8(
1833
// CHECK-NEXT: entry:
1934
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
@@ -197,6 +212,23 @@ svfloat64_t test_svldff1_f64(svbool_t pg, const float64_t *base)
197212
return SVE_ACLE_FUNC(svldff1,_f64,,)(pg, base);
198213
}
199214

215+
// CHECK-LABEL: @test_svldff1_vnum_mf8(
216+
// CHECK-NEXT: entry:
217+
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]
218+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[TMP0]])
219+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
220+
//
221+
// CPP-CHECK-LABEL: @_Z21test_svldff1_vnum_mf8u10__SVBool_tPKu6__mfp8l(
222+
// CPP-CHECK-NEXT: entry:
223+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]
224+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[TMP0]])
225+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
226+
//
227+
svmfloat8_t test_svldff1_vnum_mf8(svbool_t pg, mfloat8_t const *base, int64_t vnum)
228+
{
229+
return SVE_ACLE_FUNC(svldff1_vnum,_mf8,,)(pg, base, vnum);
230+
}
231+
200232
// CHECK-LABEL: @test_svldff1_vnum_s8(
201233
// CHECK-NEXT: entry:
202234
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]

‎clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,21 @@
1414
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
1515
#endif
1616

17+
// CHECK-LABEL: @test_svldnf1_mf8(
18+
// CHECK-NEXT: entry:
19+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
20+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
21+
//
22+
// CPP-CHECK-LABEL: @_Z16test_svldnf1_mf8u10__SVBool_tPKu6__mfp8(
23+
// CPP-CHECK-NEXT: entry:
24+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
25+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
26+
//
27+
svmfloat8_t test_svldnf1_mf8(svbool_t pg, mfloat8_t const *base)
28+
{
29+
return SVE_ACLE_FUNC(svldnf1,_mf8,,)(pg, base);
30+
}
31+
1732
// CHECK-LABEL: @test_svldnf1_s8(
1833
// CHECK-NEXT: entry:
1934
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[BASE:%.*]])
@@ -197,6 +212,23 @@ svfloat64_t test_svldnf1_f64(svbool_t pg, const float64_t *base)
197212
return SVE_ACLE_FUNC(svldnf1,_f64,,)(pg, base);
198213
}
199214

215+
// CHECK-LABEL: @test_svldnf1_vnum_mf8(
216+
// CHECK-NEXT: entry:
217+
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]
218+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[TMP0]])
219+
// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
220+
//
221+
// CPP-CHECK-LABEL: @_Z21test_svldnf1_vnum_mf8u10__SVBool_tPKu6__mfp8l(
222+
// CPP-CHECK-NEXT: entry:
223+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]
224+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], ptr [[TMP0]])
225+
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]
226+
//
227+
svmfloat8_t test_svldnf1_vnum_mf8(svbool_t pg, mfloat8_t const *base, int64_t vnum)
228+
{
229+
return SVE_ACLE_FUNC(svldnf1_vnum,_mf8,,)(pg, base, vnum);
230+
}
231+
200232
// CHECK-LABEL: @test_svldnf1_vnum_s8(
201233
// CHECK-NEXT: entry:
202234
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[BASE:%.*]], i64 [[VNUM:%.*]]

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