Address review comments

Author: phoebewang

clang/lib/CodeGen/CGBuiltin.cpp

@@ -17040,7 +17040,7 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
     Value *Store = Builder.CreateDefaultAlignedStore(VecT1, Ops[4]);
 
     // Note: Here we escape directly use x86_tilestored64_internal to store
-    // the results due to it can't make sure the Mem writen scope. This may
+    // the results due to it can't make sure the Mem written scope. This may
     // cause shapes reloads after first amx intrinsic, which current amx reg-
     // ister allocation has no ability to handle it.
 

clang/lib/Headers/amxtransposeintrin.h

@@ -32,15 +32,15 @@
 /// \headerfile <immintrin.h>
 ///
 /// \code
-/// void __tile_transposed(__tile dst, __tile src);
+/// void _tile_transposed(__tile dst, __tile src);
 /// \endcode
 ///
 /// This intrinsic corresponds to the <c> TTRANSPOSED </c> instruction.
 ///
 /// \param dst
 /// 	The destination tile. Max size is 1024 Bytes.
 /// \param src
-/// 	The 1st source tile. Max size is 1024 Bytes.
+/// 	The source tile. Max size is 1024 Bytes.
 ///
 /// \code{.operation}
 ///
@@ -238,7 +238,7 @@ static void __tile_2rpntlvwz1t1(__tile1024i *dst0, __tile1024i *dst1,
 /// \param dst
 ///    The destination tile. Max size is 1024 Bytes.
 /// \param src
-///    The 1st source tile. Max size is 1024 Bytes.
+///    The source tile. Max size is 1024 Bytes.
 __DEFAULT_FN_ATTRS_TRANSPOSE
 static void __tile_transposed(__tile1024i *dst, __tile1024i src) {
   dst->tile = _tile_transposed_internal(dst->row, dst->col, src.tile);

llvm/include/llvm/CodeGen/TileShapeInfo.h

@@ -34,14 +34,14 @@ class ShapeT {
     if (MRI)
       deduceImm(MRI);
   }
-  // When ShapeT has mult shapes, we only use Shapes (never use Row and Col)
+  // When ShapeT has multiple shapes, we only use Shapes (never use Row and Col)
   // and ImmShapes. Due to the most case is only one shape (just simply use
   // Shape.Row or Shape.Col), so here we don't merge Row and Col into vector
   // Shapes to keep the speed and code simplicity.
   // TODO: The upper solution is a temporary way to minimize current tile
   // register allocation code changes. It can not handle both Reg shape and
   // Imm shape for different shapes (e.g. shape 1 is reg shape while shape 2
-  // is imm shape). Refine me when we have more mult-tile shape instructions!
+  // is imm shape). Refine me when we have more multi-tile shape instructions!
   ShapeT(ArrayRef<MachineOperand *> ShapesOperands,
          const MachineRegisterInfo *MRI = nullptr)
       : Row(nullptr), Col(nullptr), RowImm(InvalidImmShape),
@@ -57,7 +57,7 @@ class ShapeT {
   ShapeT()
       : Row(nullptr), Col(nullptr), RowImm(InvalidImmShape),
         ColImm(InvalidImmShape) {}
-  // TODO: We need to extern cmp operator for muti-shapes if
+  // TODO: We need to extern cmp operator for multi-shapes if
   // we have requirement in the future.
   bool operator==(const ShapeT &Shape) const {
     MachineOperand *R = Shape.Row;

llvm/lib/Target/X86/X86LowerAMXType.cpp

@@ -551,7 +551,7 @@ static Instruction *createTileStore(Instruction *TileDef, Value *Ptr) {
   assert(TileDef->getType()->isX86_AMXTy() && "Not define tile!");
   auto *II = dyn_cast<IntrinsicInst>(TileDef);
   unsigned Idx = 0;
-  // Extract tile from mult tiles' def.
+  // Extract tile from multiple tiles' def.
   if (auto *Extr = dyn_cast<ExtractValueInst>(TileDef)) {
     assert(Extr->hasIndices() && "Tile extract miss index!");
     Idx = Extr->getIndices()[0];
@@ -584,7 +584,7 @@ static void replaceWithTileLoad(Use &U, Value *Ptr, bool IsPHI = false) {
     Value *PhiOp = cast<PHINode>(V)->getIncomingValue(0);
     II = cast<IntrinsicInst>(PhiOp);
   } else if (auto *Extr = dyn_cast<ExtractValueInst>(V)) {
-    // Extract tile from mult tiles' def.
+    // Extract tile from multiple tiles' def.
     assert(Extr->hasIndices() && "Tile extract miss index!");
     Idx = Extr->getIndices()[0];
     II = cast<IntrinsicInst>(Extr->getOperand(0));
@@ -1040,7 +1040,7 @@ bool X86LowerAMXCast::combineCastStore(IntrinsicInst *Cast, StoreInst *ST) {
 
   assert(Tile->getType()->isX86_AMXTy() && "Not Tile Operand!");
 
-  // TODO: Specially handle the mult-use case.
+  // TODO: Specially handle the multi-use case.
   if (Tile->getNumUses() != 1)
     return false;
 
@@ -1057,8 +1057,8 @@ bool X86LowerAMXCast::combineCastStore(IntrinsicInst *Cast, StoreInst *ST) {
     Row = II->getOperand(0);
     Col = II->getOperand(1);
   } else {
-    // Now we supported mult-tiles value in structure, so we may get tile
-    // from extracting mult-tiles structure.
+    // Now we supported multi-tiles value in structure, so we may get tile
+    // from extracting multi-tiles structure.
     // For example:
     // %6 = call { x86_amx, x86_amx } @llvm.x86.t2rpntlvwz0.internal(i16 %1,
     //      i16 %2, i16 %3, i8* %4, i64 %5)