Skip to content

Commit 5e89c26

Browse files
sc-clulzzesc-clulzze
committed
Addressed comments
1 parent ae439a6 commit 5e89c26

File tree

3 files changed

+42
-79
lines changed

3 files changed

+42
-79
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1768,7 +1768,7 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
17681768
SlotIndex NewDefSI =
17691769
LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
17701770
LiveInterval &DefLI = LIS->getInterval(VLOutput);
1771-
const auto *DefSeg = DefLI.getSegmentContaining(NewDefSI);
1771+
LiveRange::Segment *DefSeg = DefLI.getSegmentContaining(NewDefSI);
17721772
VNInfo *DefVNI = DefLI.getVNInfoAt(DefSeg->start);
17731773
DefLI.removeSegment(DefSeg->start, NewDefSI);
17741774
DefVNI->def = NewDefSI;

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -723,18 +723,18 @@ define i64 @avl_undef2() {
723723
ret i64 %1
724724
}
725725

726-
define i64 @vsetvli_vleff() {
726+
define i64 @vsetvli_vleff(ptr %s, i64 %evl) {
727727
; CHECK-LABEL: vsetvli_vleff:
728728
; CHECK: # %bb.0: # %entry
729-
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
729+
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
730730
; CHECK-NEXT: vmv.v.i v8, 0
731731
; CHECK-NEXT: .LBB37_1: # %while.body
732732
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
733-
; CHECK-NEXT: vsetivli zero, 0, e16, m1, tu, ma
733+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
734734
; CHECK-NEXT: vmv1r.v v9, v8
735-
; CHECK-NEXT: vle16ff.v v9, (zero)
736-
; CHECK-NEXT: csrr a0, vl
737-
; CHECK-NEXT: beqz a0, .LBB37_1
735+
; CHECK-NEXT: vle16ff.v v9, (a0)
736+
; CHECK-NEXT: csrr a2, vl
737+
; CHECK-NEXT: beqz a2, .LBB37_1
738738
; CHECK-NEXT: # %bb.2: # %while.end
739739
; CHECK-NEXT: li a0, 0
740740
; CHECK-NEXT: ret
@@ -747,7 +747,7 @@ while.cond:
747747
br i1 %cmp, label %while.body, label %while.end
748748

749749
while.body:
750-
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
750+
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr %s, i64 %evl)
751751
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
752752
br label %while.cond
753753

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir‎

Lines changed: 34 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -68,24 +68,6 @@
6868
ret <vscale x 1 x i64> %b
6969
}
7070

71-
define i64 @vsetvli_vleff() {
72-
entry:
73-
br label %while.cond
74-
75-
while.cond: ; preds = %while.body, %entry
76-
%new_vl.0 = phi i64 [ 0, %entry ], [ %1, %while.body ]
77-
%cmp = icmp eq i64 %new_vl.0, 0
78-
br i1 %cmp, label %while.body, label %while.end
79-
80-
while.body: ; preds = %while.cond
81-
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
82-
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
83-
br label %while.cond
84-
85-
while.end: ; preds = %while.cond
86-
ret i64 0
87-
}
88-
8971
define void @vmv_v_i_different_lmuls() {
9072
ret void
9173
}
@@ -118,6 +100,18 @@
118100
ret void
119101
}
120102

103+
define i64 @vsetvli_vleff() {
104+
bb0:
105+
br i1 poison, label %bb1, label %bb2
106+
bb1:
107+
%0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
108+
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
109+
br label %bb2
110+
bb2:
111+
%x8 = phi i64 [%1, %bb1], [0, %bb0]
112+
ret i64 %x8
113+
}
114+
121115
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
122116

123117
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, ptr nocapture, i64) #4
@@ -643,72 +637,41 @@ body: |
643637
...
644638
---
645639
name: vsetvli_vleff
646-
alignment: 4
647640
tracksRegLiveness: true
648-
registers:
649-
- { id: 0, class: gpr, preferred-register: '' }
650-
- { id: 1, class: gpr, preferred-register: '' }
651-
- { id: 2, class: gpr, preferred-register: '' }
652-
- { id: 3, class: gpr, preferred-register: '' }
653-
- { id: 4, class: gpr, preferred-register: '' }
654-
- { id: 5, class: vr, preferred-register: '%7' }
655-
- { id: 6, class: gpr, preferred-register: '' }
656-
- { id: 7, class: vr, preferred-register: '%5' }
657-
- { id: 8, class: vr, preferred-register: '' }
658-
- { id: 9, class: gpr, preferred-register: '' }
659-
frameInfo:
660-
maxAlignment: 1
661-
machineFunctionInfo: {}
662641
body: |
663642
; CHECK-LABEL: name: vsetvli_vleff
664-
; CHECK: bb.0.entry:
665-
; CHECK-NEXT: successors: %bb.1(0x80000000)
643+
; CHECK: bb.0.bb0:
644+
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
666645
; CHECK-NEXT: {{ $}}
667646
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
668-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
669-
; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
670-
; CHECK-NEXT: {{ $}}
671-
; CHECK-NEXT: bb.1.while.cond:
672-
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
673-
; CHECK-NEXT: liveins: $v8
674-
; CHECK-NEXT: {{ $}}
675-
; CHECK-NEXT: BNE [[COPY]], $x0, %bb.3
676-
; CHECK-NEXT: PseudoBR %bb.2
647+
; CHECK-NEXT: BNE $x0, $x0, %bb.2
648+
; CHECK-NEXT: PseudoBR %bb.1
677649
; CHECK-NEXT: {{ $}}
678-
; CHECK-NEXT: bb.2.while.body:
679-
; CHECK-NEXT: successors: %bb.1(0x80000000)
680-
; CHECK-NEXT: liveins: $v8
650+
; CHECK-NEXT: bb.1.bb1:
651+
; CHECK-NEXT: successors: %bb.2(0x80000000)
681652
; CHECK-NEXT: {{ $}}
682-
; CHECK-NEXT: $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
683-
; CHECK-NEXT: renamable $v9 = COPY renamable $v8, implicit $vtype
684-
; CHECK-NEXT: dead renamable $v9, $x0 = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
653+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
654+
; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
655+
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
656+
; CHECK-NEXT: dead renamable $v8, $x0 = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
685657
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = PseudoReadVL implicit $vl
686-
; CHECK-NEXT: PseudoBR %bb.1
687658
; CHECK-NEXT: {{ $}}
688-
; CHECK-NEXT: bb.3.while.end:
689-
; CHECK-NEXT: $x10 = COPY $x0
659+
; CHECK-NEXT: bb.2.bb2:
660+
; CHECK-NEXT: $x10 = COPY [[COPY]]
690661
; CHECK-NEXT: PseudoRET implicit killed $x10
691-
bb.0.entry:
692-
successors: %bb.1(0x80000000)
662+
bb.0.bb0:
663+
successors: %bb.1(0x40000000), %bb.2(0x40000000)
693664
694665
%9:gpr = COPY $x0
695-
renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
696-
697-
bb.1.while.cond:
698-
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
699-
liveins: $v8
700-
701-
BNE %9, $x0, %bb.3
702-
PseudoBR %bb.2
666+
BNE $x0, $x0, %bb.2
667+
PseudoBR %bb.1
703668
704-
bb.2.while.body:
705-
successors: %bb.1(0x80000000)
706-
liveins: $v8
669+
bb.1.bb1:
670+
successors: %bb.2(0x80000000)
707671
708-
renamable $v9 = COPY renamable $v8
709-
dead renamable $v9, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
710-
PseudoBR %bb.1
672+
renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
673+
dead renamable $v8, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
711674
712-
bb.3.while.end:
713-
$x10 = COPY $x0
675+
bb.2.bb2:
676+
$x10 = COPY %9
714677
PseudoRET implicit killed $x10

0 commit comments

Comments
 (0)