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[AMDGPU][NFC] Rename IEEEMinMax to IEEEMinMaxInsts
Also remove unused hasIEEEMinMax3 which is replaced with hasMinimum3Maximum3F32 and hasMinimum3Maximum3F16
1 parent b14e03d commit 5ec1940

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3 files changed

+5
-7
lines changed

3 files changed

+5
-7
lines changed

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2095,7 +2095,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
20952095
G_SADDO, G_SSUBO})
20962096
.lower();
20972097

2098-
if (ST.hasIEEEMinMax()) {
2098+
if (ST.hasIEEEMinMaxInsts()) {
20992099
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
21002100
.legalFor(FPTypesPK16)
21012101
.clampMaxNumElements(0, S16, 2)

llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1447,10 +1447,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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bool hasIEEEMode() const { return getGeneration() < GFX12; }
14481448

14491449
// \returns true if the target has IEEE fminimum/fmaximum instructions
1450-
bool hasIEEEMinMax() const { return getGeneration() >= GFX12; }
1451-
1452-
// \returns true if the target has IEEE fminimum3/fmaximum3 instructions
1453-
bool hasIEEEMinMax3() const { return hasIEEEMinMax(); }
1450+
bool hasIEEEMinMaxInsts() const { return getGeneration() >= GFX12; }
14541451

14551452
// \returns true if the target has WG_RR_MODE kernel descriptor mode bit
14561453
bool hasRrWGMode() const { return getGeneration() >= GFX12; }

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -877,7 +877,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
877877
if (Subtarget->hasPrefetch() && Subtarget->hasSafeSmemPrefetch())
878878
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
879879

880-
if (Subtarget->hasIEEEMinMax()) {
880+
if (Subtarget->hasIEEEMinMaxInsts()) {
881881
setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM},
882882
{MVT::f16, MVT::f32, MVT::f64, MVT::v2f16}, Legal);
883883
} else {
@@ -7023,7 +7023,8 @@ SDValue SITargetLowering::lowerFMINIMUM_FMAXIMUM(SDValue Op,
70237023
if (VT.isVector())
70247024
return splitBinaryVectorOp(Op, DAG);
70257025

7026-
assert(!Subtarget->hasIEEEMinMax() && !Subtarget->hasMinimum3Maximum3F16() &&
7026+
assert(!Subtarget->hasIEEEMinMaxInsts() &&
7027+
!Subtarget->hasMinimum3Maximum3F16() &&
70277028
Subtarget->hasMinimum3Maximum3PKF16() && VT == MVT::f16 &&
70287029
"should not need to widen f16 minimum/maximum to v2f16");
70297030

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