update format

Author: broxigarchen

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -2580,8 +2580,7 @@ def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() &&
 
 def Has16bitD16HWBug: Predicate<"Subtarget->has16bitD16HWBug()">,
   AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, Feature16bitD16HWBug)>;
-def NotHas16bitD16HWBug: Predicate<"!Subtarget->has16bitD16HWBug()"
-                                               "!Subtarget->has16bitD16HWBug()">,
+def NotHas16bitD16HWBug: Predicate<"!Subtarget->has16bitD16HWBug()">,
   AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, (not Feature16bitD16HWBug))>;
 
 def HasBF16TransInsts : Predicate<"Subtarget->hasBF16TransInsts()">,

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

@@ -38,9 +38,7 @@ bool AMDGPUSubtarget::useRealTrue16Insts() const {
   return hasTrue16BitInsts() && EnableRealTrue16Insts;
 }
 
-bool AMDGPUSubtarget::has16bitD16HWBug() const {
-  return Enable16bitD16HWBug;
-}
+bool AMDGPUSubtarget::has16bitD16HWBug() const { return Enable16bitD16HWBug; }
 
 // Returns the maximum per-workgroup LDS allocation size (in bytes) that still
 // allows the given function to achieve an occupancy of NWaves waves per

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

@@ -847,7 +847,8 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
     Result.second = Result.first + (Size / 16);
 
     if (Size == 16 && Context->ST->has16bitD16HWBug()) {
-      // Regardless of which lo16/hi16 is used, consider the full 32-bit register used.
+      // Regardless of which lo16/hi16 is used, consider the full 32-bit
+      // register used.
       if (AMDGPU::isHi16Reg(MCReg, *TRI))
         Result.first -= 1;
       else