Update llvm/lib/Target/RISCV/RISCVISelLowering.cpp

preames · topperc · web-flow · commit 5f082634407d · 2025-06-19T16:16:15.000-07:00
Co-authored-by: Craig Topper &lt;craig.topper@sifive.com&gt;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3724,7 +3724,7 @@ static SDValue lowerBuildVectorViaVID(SDValue Op, SelectionDAG &DAG,
       SplatStepVal = Log2_64(std::abs(StepNumerator));
     }
 
-    // Only emit VIDs with suitably-small steps. We use imm5 is a threshold
+    // Only emit VIDs with suitably-small steps. We use imm5 as a threshold
     // since it's the immediate value many RVV instructions accept. There is
     // no vmul.vi instruction so ensure multiply constant can fit in a
     // single addi instruction.  For the addend, we allow up to 32 bits..

Original file line number	Diff line number	Diff line change
`@@ -3724,7 +3724,7 @@ static SDValue lowerBuildVectorViaVID(SDValue Op, SelectionDAG &DAG,`
`3724`	`3724`	`SplatStepVal = Log2_64(std::abs(StepNumerator));`
`3725`	`3725`	`}`
`3726`	`3726`
`3727`		`- // Only emit VIDs with suitably-small steps. We use imm5 is a threshold`
	`3727`	`+ // Only emit VIDs with suitably-small steps. We use imm5 as a threshold`
`3728`	`3728`	`// since it's the immediate value many RVV instructions accept. There is`
`3729`	`3729`	`// no vmul.vi instruction so ensure multiply constant can fit in a`
`3730`	`3730`	`// single addi instruction. For the addend, we allow up to 32 bits..`