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mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h

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@@ -34,12 +34,4 @@ class TensorDescType;
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#define GET_OP_CLASSES
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#include <mlir/Dialect/XeGPU/IR/XeGPU.h.inc>
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namespace mlir {
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namespace xegpu {
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FailureOr<VectorType> getDistributedVectorType(VectorType originalType,
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LayoutAttr layout);
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FailureOr<VectorType> getDistributedVectorType(xegpu::TensorDescType tdescTy);
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} // namespace xegpu
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} // namespace mlir
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#endif // MLIR_DIALECT_XEGPU_IR_XEGPU_H
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@@ -1,2 +1,3 @@
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add_subdirectory(IR)
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add_subdirectory(Transforms)
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add_subdirectory(Utils)

mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp

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@@ -312,87 +312,6 @@ LogicalResult TensorDescType::verify(
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return success();
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}
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// If tensor descriptor has a layout attribute it is used in SIMT mode.
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// In this mode, the distributed vector shape is determined as follows:
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// Definitions:
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// lane_data_size = lane_data[0] × lane_data[1]
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// subgroup_size = lane_layout[0] × lane_layout[1]
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// distribution_unit_size = subgroup_size × lane_data_size
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// ---------------------------------------------------------------------
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// Case 1: Regular loads/stores.
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// ---------------------------------------------------------------------
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// The following conditions must be met:
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// * tensor_desc[0] == lane_layout[0]
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// Distributed vector is a 1D vector with shape:
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// [chunk_size]
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// ---------------------------------------------------------------------
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// Case 2: Block loads/stores
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// ---------------------------------------------------------------------
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// Additional definitions:
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// tensor_size = tensor_desc[0] * .. * tensor_desc[r-1] * array_length
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// n_distribution_units = tensor_size / distribution_unit_size
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// fragment_size = n_distribution_units * lane_data_size
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// Given above definitions, the following conditions must be met:
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// * tensor_desc[0] % (lane_layout[0] × lane_data[0]) == 0
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// * tensor_desc[1] % (lane_layout[1] × lane_data[1]) == 0
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// Distributed vector is a 1D vector with shape:
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// [fragment_size]
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FailureOr<VectorType> getDistributedVectorType(xegpu::TensorDescType tdescTy) {
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auto layout = llvm::dyn_cast_if_present<LayoutAttr>(tdescTy.getLayout());
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// It only works for subgroup level layout, which only has lane_layout
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// and lane_data, and is to distribute a SIMD code into SIMT code.
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if (!layout || !layout.isSgLayout())
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return failure();
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SmallVector<int64_t> laneData(layout.getLaneData().asArrayRef());
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SmallVector<int64_t> laneLayout(layout.getLaneLayout().asArrayRef());
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auto tdescShape = tdescTy.getShape();
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auto elementType = tdescTy.getElementType();
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// compute sgSize by multiply elements of laneLayout
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// e.g. for 2D layout, sgSize = laneLayout[0] * laneLayout[1]
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// e.g. for 1D layout, sgSize = laneLayout[0]
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auto sgSize = std::accumulate(laneLayout.begin(), laneLayout.end(), 1,
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std::multiplies<int64_t>());
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// Case 1: regular loads/stores
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auto scatterAttr = tdescTy.getEncodingAsScatterTensorDescAttr();
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if (scatterAttr) {
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auto chunkSize = scatterAttr.getChunkSize().getInt();
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// Verify if the first dimension of the tensor descriptor shape is
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// distributable.
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assert(tdescShape[0] == laneLayout[0] &&
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"tensor descriptor shape is not distributable");
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return VectorType::get({chunkSize}, elementType);
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}
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// Case 2: block loads/stores
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// Check if the tensor descriptor shape is distributable.
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int64_t tensorSize = 1;
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for (auto [tdescDim, laneDim, laneDataDim] :
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llvm::zip_equal(tdescShape, laneLayout, laneData)) {
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assert((tdescDim % (laneDim * laneDataDim) == 0) &&
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"tensor descriptor shape is not distributable");
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tensorSize *= tdescDim;
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}
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// tensorSize must be adjusted for array_length.
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tensorSize *= tdescTy.getArrayLength();
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return VectorType::get({tensorSize / sgSize}, elementType);
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}
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// Helper to get the distributed vector type for a given vector type according
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// to a given LayoutAttr.
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FailureOr<VectorType> getDistributedVectorType(VectorType originalType,
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LayoutAttr layout) {
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auto shape = originalType.getShape();
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auto helperTdescTy = xegpu::TensorDescType::get(
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shape, originalType.getElementType(),
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/*array_length=*/1, /*boundary_check=*/true,
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/*memory_space=*/xegpu::MemorySpace::Global, layout);
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return xegpu::getDistributedVectorType(helperTdescTy);
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}
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} // namespace xegpu
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} // namespace mlir
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mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt

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@@ -16,5 +16,5 @@ add_mlir_dialect_library(MLIRXeGPUTransforms
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MLIRPass
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MLIRTransforms
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MLIRGPUDialect
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MLIRXeGPUDialect
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MLIRXeGPUUtils
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)

mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp

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@@ -17,6 +17,7 @@
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#include "mlir/Dialect/XeGPU/IR/XeGPU.h"
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#include "mlir/Dialect/XeGPU/Transforms/Passes.h"
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#include "mlir/Dialect/XeGPU/Transforms/Transforms.h"
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#include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h"
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#include "mlir/IR/AffineMap.h"
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#include "mlir/IR/Attributes.h"
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#include "mlir/IR/Builders.h"

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