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ro-iro-i
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implement feedback; convert to NFC; fix formatting
1 parent 15c1d84 commit 5f3f7d2

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9 files changed

+31
-43
lines changed

9 files changed

+31
-43
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2424,13 +2424,11 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
24242424
Result = true;
24252425

24262426
else if (((SGMask & SchedGroupMask::VMEM_READ) != SchedGroupMask::NONE) &&
2427-
MI.mayLoad() &&
2428-
TII->isVMEM(MI))
2427+
MI.mayLoad() && TII->isVMEM(MI))
24292428
Result = true;
24302429

24312430
else if (((SGMask & SchedGroupMask::VMEM_WRITE) != SchedGroupMask::NONE) &&
2432-
MI.mayStore() &&
2433-
TII->isVMEM(MI))
2431+
MI.mayStore() && TII->isVMEM(MI))
24342432
Result = true;
24352433

24362434
else if (((SGMask & SchedGroupMask::DS) != SchedGroupMask::NONE) &&

‎llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,8 @@ class AMDGPUWaitSGPRHazards {
233233

234234
// SMEM or VMEM clears hazards
235235
// FIXME: adapt to add FLAT without VALU (so !isLDSDMA())?
236-
if ((SIInstrInfo::isVMEM(*MI) && !SIInstrInfo::isFLAT(*MI)) || SIInstrInfo::isSMRD(*MI)) {
236+
if ((SIInstrInfo::isVMEM(*MI) && !SIInstrInfo::isFLAT(*MI)) ||
237+
SIInstrInfo::isSMRD(*MI)) {
237238
State.VCCHazard = HazardState::None;
238239
State.SALUHazards.reset();
239240
State.VALUHazards.reset();

‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -226,8 +226,8 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
226226
if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0)
227227
return HazardType;
228228

229-
if ((SIInstrInfo::isVMEM(*MI) ||
230-
SIInstrInfo::isDS(*MI)) && checkMAILdStHazards(MI) > 0)
229+
if ((SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI)) &&
230+
checkMAILdStHazards(MI) > 0)
231231
return HazardType;
232232

233233
if (MI->isInlineAsm() && checkInlineAsmHazards(MI) > 0)
@@ -365,8 +365,7 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) {
365365
if (SIInstrInfo::isMAI(*MI))
366366
return std::max(WaitStates, checkMAIHazards(MI));
367367

368-
if (SIInstrInfo::isVMEM(*MI) ||
369-
SIInstrInfo::isDS(*MI))
368+
if (SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI))
370369
return std::max(WaitStates, checkMAILdStHazards(MI));
371370

372371
if (ST.hasGFX950Insts() && isPermlane(*MI))
@@ -1418,8 +1417,9 @@ static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF,
14181417
bool HasVmem = false;
14191418
for (auto &MBB : MF) {
14201419
for (auto &MI : MBB) {
1421-
HasLds |= SIInstrInfo::isDS(MI) || SIInstrInfo::isLDSDMA(MI);
1422-
HasVmem |= SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isLDSDMA(MI);
1420+
HasLds |= SIInstrInfo::isDS(MI);
1421+
HasVmem |= (SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isFLAT(MI)) ||
1422+
SIInstrInfo::isSegmentSpecificFLAT(MI);
14231423
if (HasLds && HasVmem)
14241424
return true;
14251425
}
@@ -1441,9 +1441,10 @@ bool GCNHazardRecognizer::fixLdsBranchVmemWARHazard(MachineInstr *MI) {
14411441
assert(!ST.hasExtendedWaitCounts());
14421442

14431443
auto IsHazardInst = [](const MachineInstr &MI) {
1444-
if (SIInstrInfo::isDS(MI) || SIInstrInfo::isLDSDMA(MI))
1444+
if (SIInstrInfo::isDS(MI))
14451445
return 1;
1446-
if (SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isLDSDMA(MI))
1446+
if ((SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isFLAT(MI)) ||
1447+
SIInstrInfo::isSegmentSpecificFLAT(MI))
14471448
return 2;
14481449
return 0;
14491450
};
@@ -2617,8 +2618,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
26172618

26182619
int WaitStatesNeeded = 0;
26192620

2620-
bool IsMem = SIInstrInfo::isVMEM(*MI) ||
2621-
SIInstrInfo::isDS(*MI);
2621+
bool IsMem = SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isDS(*MI);
26222622
bool IsMemOrExport = IsMem || SIInstrInfo::isEXP(*MI);
26232623
bool IsVALU = SIInstrInfo::isVALU(*MI);
26242624

‎llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -303,8 +303,7 @@ void AMDGPUCustomBehaviour::generateWaitCntInfo() {
303303
bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) {
304304
return MCID.TSFlags & SIInstrFlags::MUBUF ||
305305
MCID.TSFlags & SIInstrFlags::MTBUF ||
306-
MCID.TSFlags & SIInstrFlags::MIMG ||
307-
MCID.TSFlags & SIInstrFlags::FLAT;
306+
MCID.TSFlags & SIInstrFlags::MIMG || MCID.TSFlags & SIInstrFlags::FLAT;
308307
}
309308

310309
// taken from SIInstrInfo::hasModifiersSet()

‎llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,8 @@ class SIInsertHardClauses {
9797
HardClauseType getHardClauseType(const MachineInstr &MI) {
9898
if (MI.mayLoad() || (MI.mayStore() && ST->shouldClusterStores())) {
9999
if (ST->getGeneration() == AMDGPUSubtarget::GFX10) {
100-
if (SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isLDSDMA(MI)) {
100+
if ((SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isFLAT(MI)) ||
101+
SIInstrInfo::isSegmentSpecificFLAT(MI)) {
101102
if (ST->hasNSAClauseBug()) {
102103
const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
103104
if (Info && Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA)
@@ -121,7 +122,8 @@ class SIInsertHardClauses {
121122
: HARDCLAUSE_MIMG_LOAD
122123
: HARDCLAUSE_MIMG_STORE;
123124
}
124-
if (SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isLDSDMA(MI)) {
125+
if ((SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isFLAT(MI)) ||
126+
SIInstrInfo::isSegmentSpecificFLAT(MI)) {
125127
return MI.mayLoad() ? MI.mayStore() ? HARDCLAUSE_VMEM_ATOMIC
126128
: HARDCLAUSE_VMEM_LOAD
127129
: HARDCLAUSE_VMEM_STORE;

‎llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2454,8 +2454,10 @@ bool SIInsertWaitcnts::isPreheaderToFlush(
24542454
}
24552455

24562456
bool SIInsertWaitcnts::isVMEMOrFlatVMEM(const MachineInstr &MI) const {
2457-
return (SIInstrInfo::isFLAT(MI) && mayAccessVMEMThroughFlat(MI)) ||
2458-
SIInstrInfo::isVMEM(MI);
2457+
if (SIInstrInfo::isFLAT(MI))
2458+
return mayAccessVMEMThroughFlat(MI);
2459+
return SIInstrInfo::isMUBUF(MI) || SIInstrInfo::isMTBUF(MI) ||
2460+
SIInstrInfo::isImage(MI);
24592461
}
24602462

24612463
// Return true if it is better to flush the vmcnt counter in the preheader of

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -449,8 +449,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
449449
}
450450

451451
static bool isVMEM(const MachineInstr &MI) {
452-
if (isFLAT(MI))
453-
assert(usesVM_CNT(MI) && "oh no");
454452
return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI);
455453
}
456454

‎llvm/test/CodeGen/AMDGPU/hard-clauses.mir‎

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -630,29 +630,20 @@ body: |
630630
; CHECK-LABEL: name: flat_global_load
631631
; CHECK: liveins: $vgpr0_vgpr1
632632
; CHECK-NEXT: {{ $}}
633-
; CHECK-NEXT: BUNDLE implicit-def $vgpr2, implicit-def $vgpr2_lo16, implicit-def $vgpr2_hi16, implicit-def $vgpr3, implicit-def $vgpr3_lo16, implicit-def $vgpr3_hi16, implicit $vgpr0_vgpr1, implicit $exec, implicit $flat_scr {
634-
; CHECK-NEXT: S_CLAUSE 1
635-
; CHECK-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
636-
; CHECK-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
637-
; CHECK-NEXT: }
633+
; CHECK-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
634+
; CHECK-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
638635
;
639636
; GFX11-LABEL: name: flat_global_load
640637
; GFX11: liveins: $vgpr0_vgpr1
641638
; GFX11-NEXT: {{ $}}
642-
; GFX11-NEXT: BUNDLE implicit-def $vgpr2, implicit-def $vgpr2_lo16, implicit-def $vgpr2_hi16, implicit-def $vgpr3, implicit-def $vgpr3_lo16, implicit-def $vgpr3_hi16, implicit $vgpr0_vgpr1, implicit $exec, implicit $flat_scr {
643-
; GFX11-NEXT: S_CLAUSE 1
644-
; GFX11-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
645-
; GFX11-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
646-
; GFX11-NEXT: }
639+
; GFX11-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
640+
; GFX11-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
647641
;
648642
; GFX12-LABEL: name: flat_global_load
649643
; GFX12: liveins: $vgpr0_vgpr1
650644
; GFX12-NEXT: {{ $}}
651-
; GFX12-NEXT: BUNDLE implicit-def $vgpr2, implicit-def $vgpr2_lo16, implicit-def $vgpr2_hi16, implicit-def $vgpr3, implicit-def $vgpr3_lo16, implicit-def $vgpr3_hi16, implicit $vgpr0_vgpr1, implicit $exec, implicit $flat_scr {
652-
; GFX12-NEXT: S_CLAUSE 1
653-
; GFX12-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
654-
; GFX12-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
655-
; GFX12-NEXT: }
645+
; GFX12-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
646+
; GFX12-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
656647
$vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
657648
$vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr
658649
...

‎llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -269,14 +269,11 @@ body: |
269269
S_ENDPGM 0
270270
...
271271

272-
# FLAT_* instructions are "based on per-thread address (VGPR), can load/store:
273-
# global memory, LDS or scratch memory" (RDNA4 ISA)
274-
# GCN-LABEL: name: hazard_lds_branch_flat
272+
# GCN-LABEL: name: no_hazard_lds_branch_flat
275273
# GCN: bb.1:
276-
# GFX10-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0
277274
# GCN-NEXT: FLAT_LOAD_DWORD
278275
---
279-
name: hazard_lds_branch_flat
276+
name: no_hazard_lds_branch_flat
280277
body: |
281278
bb.0:
282279
successors: %bb.1

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