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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -S -passes=loop-reduce -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s |
| 3 | + |
| 4 | +define void @test(ptr %p, i64 %idx) { |
| 5 | +; CHECK-LABEL: define void @test( |
| 6 | +; CHECK-SAME: ptr [[P:%.*]], i64 [[IDX:%.*]]) { |
| 7 | +; CHECK-NEXT: [[ENTRY:.*]]: |
| 8 | +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [4 x [4 x i32]], align 16 |
| 9 | +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr [[ALLOCA]]) |
| 10 | +; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IDX]], 6 |
| 11 | +; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 48 |
| 12 | +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]] |
| 13 | +; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr nuw i8, ptr [[ALLOCA]], i64 48 |
| 14 | +; CHECK-NEXT: br label %[[LOOP:.*]] |
| 15 | +; CHECK: [[LOOP]]: |
| 16 | +; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ -8, %[[ENTRY]] ] |
| 17 | +; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i64 [[LSR_IV]], 2 |
| 18 | +; CHECK-NEXT: [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]] |
| 19 | +; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[SCEVGEP8]], i64 32 |
| 20 | +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SCEVGEP9]], align 4 |
| 21 | +; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[P]], i64 [[LSR_IV]] |
| 22 | +; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr i8, ptr [[SCEVGEP6]], i64 8 |
| 23 | +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[SCEVGEP7]], align 4 |
| 24 | +; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[SCEVGEP3]], i64 [[LSR_IV]] |
| 25 | +; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 8 |
| 26 | +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SCEVGEP5]], align 4 |
| 27 | +; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[LSR_IV]] |
| 28 | +; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 8 |
| 29 | +; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[SCEVGEP2]], align 4 |
| 30 | +; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 4 |
| 31 | +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0 |
| 32 | +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]] |
| 33 | +; CHECK: [[EXIT]]: |
| 34 | +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr [[ALLOCA]]) |
| 35 | +; CHECK-NEXT: ret void |
| 36 | +; |
| 37 | +entry: |
| 38 | + %alloca = alloca [4 x [4 x i32]], align 16 |
| 39 | + call void @llvm.lifetime.start.p0(i64 64, ptr %alloca) |
| 40 | + br label %loop |
| 41 | + |
| 42 | +loop: |
| 43 | + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %loop ] |
| 44 | + %gep1 = getelementptr [4 x [12 x [4 x [4 x i32]]]], ptr %p, i64 0, i64 0, i64 0, i64 %indvars.iv, i64 0 |
| 45 | + %0 = load i32, ptr %gep1, align 4 |
| 46 | + %gep2 = getelementptr [6 x [4 x [4 x i32]]], ptr %p, i64 0, i64 0, i64 0, i64 %indvars.iv |
| 47 | + %1 = load i32, ptr %gep2, align 4 |
| 48 | + %gep3 = getelementptr [4 x [4 x i32]], ptr %alloca, i64 0, i64 3, i64 %indvars.iv |
| 49 | + %2 = load i32, ptr %gep3, align 4 |
| 50 | + %gep4 = getelementptr [6 x [4 x [4 x i32]]], ptr %p, i64 0, i64 %idx, i64 3, i64 %indvars.iv |
| 51 | + %3 = load i32, ptr %gep4, align 4 |
| 52 | + %indvars.iv.next = add i64 %indvars.iv, 1 |
| 53 | + %exitcond.not = icmp eq i64 %indvars.iv, 1 |
| 54 | + br i1 %exitcond.not, label %exit, label %loop |
| 55 | + |
| 56 | +exit: |
| 57 | + call void @llvm.lifetime.end.p0(i64 64, ptr %alloca) |
| 58 | + ret void |
| 59 | +} |
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