Skip to content

Commit 5f72f2c

Browse files
authored
AMDGPU: Remove large, negative AddedComplexity from minimum/maximum patterns (#119795)
1 parent 82459ec commit 5f72f2c

File tree

2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -948,7 +948,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
948948

949949
// On GFX12 MIN/MAX instructions do not read MODE register.
950950
let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 1, isCommutable = 1,
951-
isReMaterializable = 1, SchedRW = [WriteSFPU] in {
951+
isReMaterializable = 1, SchedRW = [WriteSFPU], AddedComplexity = 17 in {
952952
def S_MINIMUM_F32 : SOP2_F32_Inst<"s_minimum_f32", fminimum>;
953953
def S_MAXIMUM_F32 : SOP2_F32_Inst<"s_maximum_f32", fmaximum>;
954954
def S_MINIMUM_F16 : SOP2_F16_Inst<"s_minimum_f16", fminimum>;

llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", V_MUL_PROF<VOP_I32_I32_I32>>;
167167
defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>;
168168
} // End SchedRW = [WriteIntMul]
169169

170-
let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
170+
let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1 in {
171171
defm V_MINIMUM_F32 : VOP3Inst <"v_minimum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fminimum>>;
172172
defm V_MAXIMUM_F32 : VOP3Inst <"v_maximum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fmaximum>>;
173173
defm V_MINIMUM_F16 : VOP3Inst <"v_minimum_f16", VOP3_Profile<VOP_F16_F16_F16>, DivergentBinFrag<fminimum>>;
@@ -177,7 +177,7 @@ let SchedRW = [WriteDoubleAdd] in {
177177
defm V_MINIMUM_F64 : VOP3Inst <"v_minimum_f64", VOP3_Profile<VOP_F64_F64_F64>, fminimum>;
178178
defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaximum>;
179179
} // End SchedRW = [WriteDoubleAdd]
180-
} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
180+
} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1
181181

182182
} // End isReMaterializable = 1
183183

@@ -1560,7 +1560,7 @@ class MinimumMaximumByMinimum3Maximum3<SDPatternOperator node, ValueType vt,
15601560
>;
15611561

15621562
// Prefer the real 2 operand form if legal
1563-
let SubtargetPredicate = HasMinimum3Maximum3F32, AddedComplexity = -1000 in {
1563+
let SubtargetPredicate = HasMinimum3Maximum3F32 in {
15641564
def : MinimumMaximumByMinimum3Maximum3<fminimum, f32, V_MINIMUM3_F32_e64>;
15651565
def : MinimumMaximumByMinimum3Maximum3<fmaximum, f32, V_MAXIMUM3_F32_e64>;
15661566
}

0 commit comments

Comments
 (0)