Update tests

Author: lukel97

llvm/test/MachineVerifier/RISCV/subreg-liveness.mir

@@ -19,8 +19,8 @@ body:             |
     ; CHECK: liveins: $v0, $v8, $v9, $v10, $v11
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
-    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16
+    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype
     renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
-    $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16
+    $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype
 
 ...

llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s

@@ -293,12 +293,12 @@ vfmv.f.s f7, v16
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      280
-# CHECK-NEXT: Total Cycles:      523
+# CHECK-NEXT: Total Cycles:      524
 # CHECK-NEXT: Total uOps:        280
 
 # CHECK:      Dispatch Width:    3
-# CHECK-NEXT: uOps Per Cycle:    0.54
-# CHECK-NEXT: IPC:               0.54
+# CHECK-NEXT: uOps Per Cycle:    0.53
+# CHECK-NEXT: IPC:               0.53
 # CHECK-NEXT: Block RThroughput: 512.0
 
 # CHECK:      Instruction Info:

llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s

@@ -260,12 +260,12 @@ vmv8r.v	v8, v16
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      256
-# CHECK-NEXT: Total Cycles:      237
+# CHECK-NEXT: Total Cycles:      255
 # CHECK-NEXT: Total uOps:        256
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.08
-# CHECK-NEXT: IPC:               1.08
+# CHECK-NEXT: uOps Per Cycle:    1.00
+# CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 240.0
 
 # CHECK:      Instruction Info: