Clean up code.

Co-authored-by: Matt Arsenault <[email protected]>

Author: LU-JOHN

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5956,6 +5956,10 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B64);
   case AMDGPU::S_UADDO_PSEUDO:
   case AMDGPU::S_USUBO_PSEUDO: {
+<<<<<<< HEAD
+=======
+    const DebugLoc &DL = MI.getDebugLoc();
+>>>>>>> 27321ddcdbe2 (Clean up code.)
     MachineOperand &Dest0 = MI.getOperand(0);
     MachineOperand &Dest1 = MI.getOperand(1);
     MachineOperand &Src0 = MI.getOperand(2);
@@ -5970,11 +5974,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
         .add(Src1);
     // clang-format on
 
-    const TargetRegisterClass *Dest1RC = MRI.getRegClass(Dest1.getReg());
-    unsigned Dest1Size = TRI->getRegSizeInBits(*Dest1RC);
-    assert(Dest1Size == 64 || Dest1Size == 32);
     unsigned SelOpc =
-        (Dest1Size == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
+        Subtarget->isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
     BuildMI(*BB, MI, DL, TII->get(SelOpc), Dest1.getReg()).addImm(1).addImm(0);
 
     MI.eraseFromParent();