FeaturePermissiveZalrsc does not imply FeatureStdExtZalrsc

Author: slachowsky

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1923,8 +1923,7 @@ def HasAtomicLdSt
 def FeaturePermissiveZalrsc
     : SubtargetFeature<
           "permissive-zalrsc", "HasPermissiveZalrsc", "true",
-          "Implementation permits non-base instructions between LR/SC pairs",
-          [FeatureStdExtZalrsc]>;
+          "Implementation permits non-base instructions between LR/SC pairs">;
 
 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "AllowTaggedGlobals",

llvm/test/CodeGen/RISCV/atomic-rmw-minmax.ll

@@ -1,16 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+b,+zalrsc -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32IB-COMMON,RV32IB-ZALRSC %s
-; RUN: llc -mtriple=riscv32 -mattr=+b,+permissive-zalrsc -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+b,+zalrsc,+permissive-zalrsc -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32IB-COMMON,RV32IB-ZALRSC-PERM %s
-; RUN: llc -mtriple=riscv32 -mattr=+b,+permissive-zalrsc,+a -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+b,+zalrsc,+permissive-zalrsc,+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32IB-COMMON,RV32IAB %s
 ;
 ; RUN: llc -mtriple=riscv64 -mattr=+b,+zalrsc -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64IB-ZALRSC %s
-; RUN: llc -mtriple=riscv64 -mattr=+b,+permissive-zalrsc -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+b,+zalrsc,+permissive-zalrsc -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64IB-ZALRSC-PERM %s
-; RUN: llc -mtriple=riscv64 -mattr=+b,+permissive-zalrsc,+a -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+b,+zalrsc,+permissive-zalrsc,+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64IAB %s
 
 define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {