Move AArch64ISD selection into TableGen

Author: mrkajetanp

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -424,7 +424,6 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
   void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
   void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
                              unsigned Opc_rr, unsigned Opc_ri);
-  void SelectFCVT_FPTOINT_Half(SDNode *N, unsigned Opc);
   std::tuple<unsigned, SDValue, SDValue>
   findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr, unsigned Opc_ri,
                            const SDValue &OldBase, const SDValue &OldOffset,
@@ -2537,24 +2536,6 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
   ReplaceNode(N, St);
 }
 
-// Select f16 -> i16 conversions
-// Since i16 is an illegal type, we return the converted bit pattern in a f32
-// which can then be bitcast to i32 and truncated as needed.
-void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
-  SDLoc DL(N);
-  SDValue SrcVal = N->getOperand(0);
-  SDNode *Cvt = CurDAG->getMachineNode(Opc, DL, MVT::f16, SrcVal);
-  SDValue Sign = CurDAG->getTargetConstant(-1, DL, MVT::i64);
-  SDValue Hsub = CurDAG->getTargetConstant(AArch64::hsub, DL, MVT::i32);
-  SDNode *SubregToReg = CurDAG->getMachineNode(
-      TargetOpcode::SUBREG_TO_REG, DL, MVT::v8f16, Sign, SDValue(Cvt, 0), Hsub);
-  SDValue Ssub = CurDAG->getTargetConstant(AArch64::ssub, DL, MVT::i32);
-  SDNode *Extract =
-      CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f32,
-                             SDValue(SubregToReg, 0), Ssub);
-  ReplaceNode(N, Extract);
-}
-
 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
                                        unsigned &Opc, SDValue &Opd0,
                                        unsigned &LSB, unsigned &MSB,
@@ -7378,14 +7359,6 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
     }
     break;
   }
-  case AArch64ISD::FCVTZS_HALF: {
-    SelectFCVT_FPTOINT_Half(Node, AArch64::FCVTZSv1f16);
-    return;
-  }
-  case AArch64ISD::FCVTZU_HALF: {
-    SelectFCVT_FPTOINT_Half(Node, AArch64::FCVTZUv1f16);
-    return;
-  }
   }
 
   // Select the default instruction

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -6542,6 +6542,18 @@ defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
 def : Pat<(v1i64 (AArch64vashr (v1i64 V64:$Rn), (i32 63))),
           (CMLTv1i64rz V64:$Rn)>;
 
+// f16 -> s16 conversions leave the bit pattern in a f32
+class F16ToS16ScalarPat<SDNode cvt_isd, BaseSIMDTwoScalar instr>
+    : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))),
+    (EXTRACT_SUBREG
+     (v8f16 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub)),
+     ssub)>;
+
+let Predicates = [HasFullFP16] in {
+def : F16ToS16ScalarPat<AArch64fcvtzs_half, FCVTZSv1f16>;
+def : F16ToS16ScalarPat<AArch64fcvtzu_half, FCVTZUv1f16>;
+}
+
 // Round FP64 to BF16.
 let Predicates = [HasNEONandIsStreamingSafe, HasBF16] in
 def : Pat<(bf16 (any_fpround (f64 FPR64:$Rn))),