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LoongArch: Remove fixup kinds that map to relocation types
Follow-up to 40789ce ("MCFixup: Move relocation values before FK_NONE")
1 parent dca0ccf commit 609586f

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5 files changed

+55
-158
lines changed

5 files changed

+55
-158
lines changed

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -217,9 +217,7 @@ bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
217217
MCSection *Sec = AF.getParent();
218218
MCContext &Ctx = Asm.getContext();
219219
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
220-
// Create fixup_loongarch_align fixup.
221-
MCFixup Fixup =
222-
MCFixup::create(0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_align));
220+
MCFixup Fixup = MCFixup::create(0, Dummy, ELF::R_LARCH_ALIGN);
223221
unsigned MaxBytesToEmit = AF.getMaxBytesToEmit();
224222

225223
auto createExtendedValue = [&]() {

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,9 +34,8 @@ class LoongArchAsmBackend : public MCAsmBackend {
3434
public:
3535
LoongArchAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
3636
const MCTargetOptions &Options)
37-
: MCAsmBackend(llvm::endianness::little,
38-
LoongArch::fixup_loongarch_relax),
39-
STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {}
37+
: MCAsmBackend(llvm::endianness::little, ELF::R_LARCH_RELAX), STI(STI),
38+
OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {}
4039
~LoongArchAsmBackend() override {}
4140

4241
bool handleAddSubRelocations(const MCAssembler &Asm, const MCFragment &F,

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -110,9 +110,6 @@ unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
110110
return ELF::R_LARCH_TLS_LE64_LO20;
111111
case LoongArch::fixup_loongarch_tls_le64_hi12:
112112
return ELF::R_LARCH_TLS_LE64_HI12;
113-
case LoongArch::fixup_loongarch_call36:
114-
return ELF::R_LARCH_CALL36;
115-
// TODO: Handle more fixup-kinds.
116113
}
117114
}
118115

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h‎

Lines changed: 0 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -51,102 +51,6 @@ enum Fixups {
5151
// LoongArchAsmBackend::applyFixup.
5252
fixup_loongarch_invalid,
5353
NumTargetFixupKinds = fixup_loongarch_invalid - FirstTargetFixupKind,
54-
55-
// Define fixups for force relocation as FirstRelocationKind+V
56-
// represents the relocation type with number V.
57-
// 20-bit fixup corresponding to %pc_hi20(foo) for instruction pcalau12i.
58-
fixup_loongarch_pcala_hi20 = ELF::R_LARCH_PCALA_HI20,
59-
// 12-bit fixup corresponding to %pc_lo12(foo) for instructions like addi.w/d.
60-
fixup_loongarch_pcala_lo12,
61-
// 20-bit fixup corresponding to %pc64_lo20(foo) for instruction lu32i.d.
62-
fixup_loongarch_pcala64_lo20,
63-
// 12-bit fixup corresponding to %pc64_hi12(foo) for instruction lu52i.d.
64-
fixup_loongarch_pcala64_hi12,
65-
// 20-bit fixup corresponding to %got_pc_hi20(foo) for instruction pcalau12i.
66-
fixup_loongarch_got_pc_hi20,
67-
// 12-bit fixup corresponding to %got_pc_lo12(foo) for instructions
68-
// ld.w/ld.d/add.d.
69-
fixup_loongarch_got_pc_lo12,
70-
// 20-bit fixup corresponding to %got64_pc_lo20(foo) for instruction lu32i.d.
71-
fixup_loongarch_got64_pc_lo20,
72-
// 12-bit fixup corresponding to %got64_pc_hi12(foo) for instruction lu52i.d.
73-
fixup_loongarch_got64_pc_hi12,
74-
// 20-bit fixup corresponding to %got_hi20(foo) for instruction lu12i.w.
75-
fixup_loongarch_got_hi20,
76-
// 12-bit fixup corresponding to %got_lo12(foo) for instruction ori.
77-
fixup_loongarch_got_lo12,
78-
// 20-bit fixup corresponding to %got64_lo20(foo) for instruction lu32i.d.
79-
fixup_loongarch_got64_lo20,
80-
// 12-bit fixup corresponding to %got64_hi12(foo) for instruction lu52i.d.
81-
fixup_loongarch_got64_hi12,
82-
// Skip R_LARCH_TLS_LE_*.
83-
// 20-bit fixup corresponding to %ie_pc_hi20(foo) for instruction pcalau12i.
84-
fixup_loongarch_tls_ie_pc_hi20 = ELF::R_LARCH_TLS_IE_PC_HI20,
85-
// 12-bit fixup corresponding to %ie_pc_lo12(foo) for instructions
86-
// ld.w/ld.d/add.d.
87-
fixup_loongarch_tls_ie_pc_lo12,
88-
// 20-bit fixup corresponding to %ie64_pc_lo20(foo) for instruction lu32i.d.
89-
fixup_loongarch_tls_ie64_pc_lo20,
90-
// 12-bit fixup corresponding to %ie64_pc_hi12(foo) for instruction lu52i.d.
91-
fixup_loongarch_tls_ie64_pc_hi12,
92-
// 20-bit fixup corresponding to %ie_hi20(foo) for instruction lu12i.w.
93-
fixup_loongarch_tls_ie_hi20,
94-
// 12-bit fixup corresponding to %ie_lo12(foo) for instruction ori.
95-
fixup_loongarch_tls_ie_lo12,
96-
// 20-bit fixup corresponding to %ie64_lo20(foo) for instruction lu32i.d.
97-
fixup_loongarch_tls_ie64_lo20,
98-
// 12-bit fixup corresponding to %ie64_hi12(foo) for instruction lu52i.d.
99-
fixup_loongarch_tls_ie64_hi12,
100-
// 20-bit fixup corresponding to %ld_pc_hi20(foo) for instruction pcalau12i.
101-
fixup_loongarch_tls_ld_pc_hi20,
102-
// 20-bit fixup corresponding to %ld_hi20(foo) for instruction lu12i.w.
103-
fixup_loongarch_tls_ld_hi20,
104-
// 20-bit fixup corresponding to %gd_pc_hi20(foo) for instruction pcalau12i.
105-
fixup_loongarch_tls_gd_pc_hi20,
106-
// 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
107-
fixup_loongarch_tls_gd_hi20,
108-
// Generate an R_LARCH_RELAX which indicates the linker may relax here.
109-
fixup_loongarch_relax = ELF::R_LARCH_RELAX,
110-
// Generate an R_LARCH_ALIGN which indicates the linker may fixup align here.
111-
fixup_loongarch_align = ELF::R_LARCH_ALIGN,
112-
// 20-bit fixup corresponding to %pcrel_20(foo) for instruction pcaddi.
113-
fixup_loongarch_pcrel20_s2,
114-
// 36-bit fixup corresponding to %call36(foo) for a pair instructions:
115-
// pcaddu18i+jirl.
116-
fixup_loongarch_call36 = ELF::R_LARCH_CALL36,
117-
// 20-bit fixup corresponding to %desc_pc_hi20(foo) for instruction pcalau12i.
118-
fixup_loongarch_tls_desc_pc_hi20 = ELF::R_LARCH_TLS_DESC_PC_HI20,
119-
// 12-bit fixup corresponding to %desc_pc_lo12(foo) for instructions like
120-
// addi.w/d.
121-
fixup_loongarch_tls_desc_pc_lo12,
122-
// 20-bit fixup corresponding to %desc64_pc_lo20(foo) for instruction lu32i.d.
123-
fixup_loongarch_tls_desc64_pc_lo20,
124-
// 12-bit fixup corresponding to %desc64_pc_hi12(foo) for instruction lu52i.d.
125-
fixup_loongarch_tls_desc64_pc_hi12,
126-
// 20-bit fixup corresponding to %desc_hi20(foo) for instruction lu12i.w.
127-
fixup_loongarch_tls_desc_hi20,
128-
// 12-bit fixup corresponding to %desc_lo12(foo) for instruction ori.
129-
fixup_loongarch_tls_desc_lo12,
130-
// 20-bit fixup corresponding to %desc64_lo20(foo) for instruction lu32i.d.
131-
fixup_loongarch_tls_desc64_lo20,
132-
// 12-bit fixup corresponding to %desc64_hi12(foo) for instruction lu52i.d.
133-
fixup_loongarch_tls_desc64_hi12,
134-
// 12-bit fixup corresponding to %desc_ld(foo) for instruction ld.w/d.
135-
fixup_loongarch_tls_desc_ld,
136-
// 12-bit fixup corresponding to %desc_call(foo) for instruction jirl.
137-
fixup_loongarch_tls_desc_call,
138-
// 20-bit fixup corresponding to %le_hi20_r(foo) for instruction lu12i.w.
139-
fixup_loongarch_tls_le_hi20_r,
140-
// Fixup corresponding to %le_add_r(foo) for instruction PseudoAddTPRel_W/D.
141-
fixup_loongarch_tls_le_add_r,
142-
// 12-bit fixup corresponding to %le_lo12_r(foo) for instruction addi.w/d.
143-
fixup_loongarch_tls_le_lo12_r,
144-
// 20-bit fixup corresponding to %ld_pcrel_20(foo) for instruction pcaddi.
145-
fixup_loongarch_tls_ld_pcrel20_s2,
146-
// 20-bit fixup corresponding to %gd_pcrel_20(foo) for instruction pcaddi.
147-
fixup_loongarch_tls_gd_pcrel20_s2,
148-
// 20-bit fixup corresponding to %desc_pcrel_20(foo) for instruction pcaddi.
149-
fixup_loongarch_tls_desc_pcrel20_s2,
15054
};
15155
} // end namespace LoongArch
15256
} // end namespace llvm

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp‎

Lines changed: 52 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,7 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
128128
bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
129129
const MCExpr *Expr = MO.getExpr();
130130
MCExpr::ExprKind Kind = Expr->getKind();
131-
LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
131+
unsigned FixupKind = LoongArch::fixup_loongarch_invalid;
132132
if (Kind == MCExpr::Target) {
133133
const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
134134

@@ -163,142 +163,142 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
163163
FixupKind = LoongArch::fixup_loongarch_abs64_hi12;
164164
break;
165165
case LoongArchMCExpr::VK_PCALA_HI20:
166-
FixupKind = LoongArch::fixup_loongarch_pcala_hi20;
166+
FixupKind = ELF::R_LARCH_PCALA_HI20;
167167
break;
168168
case LoongArchMCExpr::VK_PCALA_LO12:
169-
FixupKind = LoongArch::fixup_loongarch_pcala_lo12;
169+
FixupKind = ELF::R_LARCH_PCALA_LO12;
170170
break;
171171
case LoongArchMCExpr::VK_PCALA64_LO20:
172-
FixupKind = LoongArch::fixup_loongarch_pcala64_lo20;
172+
FixupKind = ELF::R_LARCH_PCALA64_LO20;
173173
break;
174174
case LoongArchMCExpr::VK_PCALA64_HI12:
175-
FixupKind = LoongArch::fixup_loongarch_pcala64_hi12;
175+
FixupKind = ELF::R_LARCH_PCALA64_HI12;
176176
break;
177177
case LoongArchMCExpr::VK_GOT_PC_HI20:
178-
FixupKind = LoongArch::fixup_loongarch_got_pc_hi20;
178+
FixupKind = ELF::R_LARCH_GOT_PC_HI20;
179179
break;
180180
case LoongArchMCExpr::VK_GOT_PC_LO12:
181-
FixupKind = LoongArch::fixup_loongarch_got_pc_lo12;
181+
FixupKind = ELF::R_LARCH_GOT_PC_LO12;
182182
break;
183183
case LoongArchMCExpr::VK_GOT64_PC_LO20:
184-
FixupKind = LoongArch::fixup_loongarch_got64_pc_lo20;
184+
FixupKind = ELF::R_LARCH_GOT64_PC_LO20;
185185
break;
186186
case LoongArchMCExpr::VK_GOT64_PC_HI12:
187-
FixupKind = LoongArch::fixup_loongarch_got64_pc_hi12;
187+
FixupKind = ELF::R_LARCH_GOT64_PC_HI12;
188188
break;
189189
case LoongArchMCExpr::VK_GOT_HI20:
190-
FixupKind = LoongArch::fixup_loongarch_got_hi20;
190+
FixupKind = ELF::R_LARCH_GOT_HI20;
191191
break;
192192
case LoongArchMCExpr::VK_GOT_LO12:
193-
FixupKind = LoongArch::fixup_loongarch_got_lo12;
193+
FixupKind = ELF::R_LARCH_GOT_LO12;
194194
break;
195195
case LoongArchMCExpr::VK_GOT64_LO20:
196-
FixupKind = LoongArch::fixup_loongarch_got64_lo20;
196+
FixupKind = ELF::R_LARCH_GOT64_LO20;
197197
break;
198198
case LoongArchMCExpr::VK_GOT64_HI12:
199-
FixupKind = LoongArch::fixup_loongarch_got64_hi12;
199+
FixupKind = ELF::R_LARCH_GOT64_HI12;
200200
break;
201201
case LoongArchMCExpr::VK_TLS_LE_HI20:
202-
FixupKind = LoongArch::fixup_loongarch_tls_le_hi20;
202+
FixupKind = ELF::R_LARCH_TLS_LE_HI20;
203203
break;
204204
case LoongArchMCExpr::VK_TLS_LE_LO12:
205-
FixupKind = LoongArch::fixup_loongarch_tls_le_lo12;
205+
FixupKind = ELF::R_LARCH_TLS_LE_LO12;
206206
break;
207207
case LoongArchMCExpr::VK_TLS_LE64_LO20:
208-
FixupKind = LoongArch::fixup_loongarch_tls_le64_lo20;
208+
FixupKind = ELF::R_LARCH_TLS_LE64_LO20;
209209
break;
210210
case LoongArchMCExpr::VK_TLS_LE64_HI12:
211-
FixupKind = LoongArch::fixup_loongarch_tls_le64_hi12;
211+
FixupKind = ELF::R_LARCH_TLS_LE64_HI12;
212212
break;
213213
case LoongArchMCExpr::VK_TLS_IE_PC_HI20:
214-
FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_hi20;
214+
FixupKind = ELF::R_LARCH_TLS_IE_PC_HI20;
215215
break;
216216
case LoongArchMCExpr::VK_TLS_IE_PC_LO12:
217-
FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_lo12;
217+
FixupKind = ELF::R_LARCH_TLS_IE_PC_LO12;
218218
break;
219219
case LoongArchMCExpr::VK_TLS_IE64_PC_LO20:
220-
FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_lo20;
220+
FixupKind = ELF::R_LARCH_TLS_IE64_PC_LO20;
221221
break;
222222
case LoongArchMCExpr::VK_TLS_IE64_PC_HI12:
223-
FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_hi12;
223+
FixupKind = ELF::R_LARCH_TLS_IE64_PC_HI12;
224224
break;
225225
case LoongArchMCExpr::VK_TLS_IE_HI20:
226-
FixupKind = LoongArch::fixup_loongarch_tls_ie_hi20;
226+
FixupKind = ELF::R_LARCH_TLS_IE_HI20;
227227
break;
228228
case LoongArchMCExpr::VK_TLS_IE_LO12:
229-
FixupKind = LoongArch::fixup_loongarch_tls_ie_lo12;
229+
FixupKind = ELF::R_LARCH_TLS_IE_LO12;
230230
break;
231231
case LoongArchMCExpr::VK_TLS_IE64_LO20:
232-
FixupKind = LoongArch::fixup_loongarch_tls_ie64_lo20;
232+
FixupKind = ELF::R_LARCH_TLS_IE64_LO20;
233233
break;
234234
case LoongArchMCExpr::VK_TLS_IE64_HI12:
235-
FixupKind = LoongArch::fixup_loongarch_tls_ie64_hi12;
235+
FixupKind = ELF::R_LARCH_TLS_IE64_HI12;
236236
break;
237237
case LoongArchMCExpr::VK_TLS_LD_PC_HI20:
238-
FixupKind = LoongArch::fixup_loongarch_tls_ld_pc_hi20;
238+
FixupKind = ELF::R_LARCH_TLS_LD_PC_HI20;
239239
break;
240240
case LoongArchMCExpr::VK_TLS_LD_HI20:
241-
FixupKind = LoongArch::fixup_loongarch_tls_ld_hi20;
241+
FixupKind = ELF::R_LARCH_TLS_LD_HI20;
242242
break;
243243
case LoongArchMCExpr::VK_TLS_GD_PC_HI20:
244-
FixupKind = LoongArch::fixup_loongarch_tls_gd_pc_hi20;
244+
FixupKind = ELF::R_LARCH_TLS_GD_PC_HI20;
245245
break;
246246
case LoongArchMCExpr::VK_TLS_GD_HI20:
247-
FixupKind = LoongArch::fixup_loongarch_tls_gd_hi20;
247+
FixupKind = ELF::R_LARCH_TLS_GD_HI20;
248248
break;
249249
case LoongArchMCExpr::VK_CALL36:
250-
FixupKind = LoongArch::fixup_loongarch_call36;
250+
FixupKind = ELF::R_LARCH_CALL36;
251251
RelaxCandidate = true;
252252
break;
253253
case LoongArchMCExpr::VK_TLS_DESC_PC_HI20:
254-
FixupKind = LoongArch::fixup_loongarch_tls_desc_pc_hi20;
254+
FixupKind = ELF::R_LARCH_TLS_DESC_PC_HI20;
255255
break;
256256
case LoongArchMCExpr::VK_TLS_DESC_PC_LO12:
257-
FixupKind = LoongArch::fixup_loongarch_tls_desc_pc_lo12;
257+
FixupKind = ELF::R_LARCH_TLS_DESC_PC_LO12;
258258
break;
259259
case LoongArchMCExpr::VK_TLS_DESC64_PC_LO20:
260-
FixupKind = LoongArch::fixup_loongarch_tls_desc64_pc_lo20;
260+
FixupKind = ELF::R_LARCH_TLS_DESC64_PC_LO20;
261261
break;
262262
case LoongArchMCExpr::VK_TLS_DESC64_PC_HI12:
263-
FixupKind = LoongArch::fixup_loongarch_tls_desc64_pc_hi12;
263+
FixupKind = ELF::R_LARCH_TLS_DESC64_PC_HI12;
264264
break;
265265
case LoongArchMCExpr::VK_TLS_DESC_HI20:
266-
FixupKind = LoongArch::fixup_loongarch_tls_desc_hi20;
266+
FixupKind = ELF::R_LARCH_TLS_DESC_HI20;
267267
break;
268268
case LoongArchMCExpr::VK_TLS_DESC_LO12:
269-
FixupKind = LoongArch::fixup_loongarch_tls_desc_lo12;
269+
FixupKind = ELF::R_LARCH_TLS_DESC_LO12;
270270
break;
271271
case LoongArchMCExpr::VK_TLS_DESC64_LO20:
272-
FixupKind = LoongArch::fixup_loongarch_tls_desc64_lo20;
272+
FixupKind = ELF::R_LARCH_TLS_DESC64_LO20;
273273
break;
274274
case LoongArchMCExpr::VK_TLS_DESC64_HI12:
275-
FixupKind = LoongArch::fixup_loongarch_tls_desc64_hi12;
275+
FixupKind = ELF::R_LARCH_TLS_DESC64_HI12;
276276
break;
277277
case LoongArchMCExpr::VK_TLS_DESC_LD:
278-
FixupKind = LoongArch::fixup_loongarch_tls_desc_ld;
278+
FixupKind = ELF::R_LARCH_TLS_DESC_LD;
279279
break;
280280
case LoongArchMCExpr::VK_TLS_DESC_CALL:
281-
FixupKind = LoongArch::fixup_loongarch_tls_desc_call;
281+
FixupKind = ELF::R_LARCH_TLS_DESC_CALL;
282282
break;
283283
case LoongArchMCExpr::VK_TLS_LE_HI20_R:
284-
FixupKind = LoongArch::fixup_loongarch_tls_le_hi20_r;
284+
FixupKind = ELF::R_LARCH_TLS_LE_HI20_R;
285285
RelaxCandidate = true;
286286
break;
287287
case LoongArchMCExpr::VK_TLS_LE_LO12_R:
288-
FixupKind = LoongArch::fixup_loongarch_tls_le_lo12_r;
288+
FixupKind = ELF::R_LARCH_TLS_LE_LO12_R;
289289
RelaxCandidate = true;
290290
break;
291291
case LoongArchMCExpr::VK_PCREL20_S2:
292-
FixupKind = LoongArch::fixup_loongarch_pcrel20_s2;
292+
FixupKind = ELF::R_LARCH_PCREL20_S2;
293293
break;
294294
case LoongArchMCExpr::VK_TLS_LD_PCREL20_S2:
295-
FixupKind = LoongArch::fixup_loongarch_tls_ld_pcrel20_s2;
295+
FixupKind = ELF::R_LARCH_TLS_LD_PCREL20_S2;
296296
break;
297297
case LoongArchMCExpr::VK_TLS_GD_PCREL20_S2:
298-
FixupKind = LoongArch::fixup_loongarch_tls_gd_pcrel20_s2;
298+
FixupKind = ELF::R_LARCH_TLS_GD_PCREL20_S2;
299299
break;
300300
case LoongArchMCExpr::VK_TLS_DESC_PCREL20_S2:
301-
FixupKind = LoongArch::fixup_loongarch_tls_desc_pcrel20_s2;
301+
FixupKind = ELF::R_LARCH_TLS_DESC_PCREL20_S2;
302302
break;
303303
}
304304
} else if (Kind == MCExpr::SymbolRef &&
@@ -338,8 +338,8 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
338338
// hint.
339339
if (EnableRelax && RelaxCandidate) {
340340
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
341-
Fixups.push_back(MCFixup::create(
342-
0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
341+
Fixups.push_back(
342+
MCFixup::create(0, Dummy, ELF::R_LARCH_RELAX, MI.getLoc()));
343343
}
344344

345345
return 0;
@@ -388,15 +388,14 @@ void LoongArchMCCodeEmitter::expandAddTPRel(const MCInst &MI,
388388
"Expected %le_add_r relocation on TP-relative symbol");
389389

390390
// Emit the correct %le_add_r relocation for the symbol.
391-
Fixups.push_back(MCFixup::create(
392-
0, Expr, MCFixupKind(LoongArch::fixup_loongarch_tls_le_add_r),
393-
MI.getLoc()));
391+
Fixups.push_back(
392+
MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R, MI.getLoc()));
394393

395394
// Emit R_LARCH_RELAX for %le_add_r when the relax feature is enabled.
396395
if (STI.hasFeature(LoongArch::FeatureRelax)) {
397396
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
398-
Fixups.push_back(MCFixup::create(
399-
0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
397+
Fixups.push_back(
398+
MCFixup::create(0, Dummy, ELF::R_LARCH_RELAX, MI.getLoc()));
400399
}
401400

402401
// Emit a normal ADD instruction with the given operands.

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