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michaelmaitlandmichaelmaitland
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[RISCV] Split Widening convert to FP pseudos by SEW
1 parent 2e0e3b0 commit 60a1158

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7 files changed

+168
-71
lines changed

7 files changed

+168
-71
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 86 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -17642,8 +17642,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
1764217642

1764317643
static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
1764417644
MachineBasicBlock *BB,
17645-
unsigned CVTXOpc,
17646-
unsigned CVTFOpc) {
17645+
unsigned CVTXOpc) {
1764717646
DebugLoc DL = MI.getDebugLoc();
1764817647

1764917648
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
@@ -17674,6 +17673,85 @@ static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
1767417673
/*IsImp*/ true));
1767517674

1767617675
// Emit a VFCVT_F_X
17676+
RISCVII::VLMUL LMul = RISCVII::getLMul(MI.getDesc().TSFlags);
17677+
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
17678+
// There is no E8 variant for VFCVT_F_X.
17679+
assert(Log2SEW >= 4);
17680+
// Since MI (VFROUND) isn't SEW specific, we cannot use a macro to make
17681+
// handling of different (LMUL, SEW) pairs easier because we need to pull the
17682+
// SEW immediate from MI, and that information is not avaliable during macro
17683+
// expansion.
17684+
unsigned CVTFOpc;
17685+
if (Log2SEW == 4) {
17686+
switch (LMul) {
17687+
case RISCVII::LMUL_1:
17688+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E16_MASK;
17689+
break;
17690+
case RISCVII::LMUL_2:
17691+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E16_MASK;
17692+
break;
17693+
case RISCVII::LMUL_4:
17694+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E16_MASK;
17695+
break;
17696+
case RISCVII::LMUL_8:
17697+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E16_MASK;
17698+
break;
17699+
case RISCVII::LMUL_F2:
17700+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E16_MASK;
17701+
break;
17702+
case RISCVII::LMUL_F4:
17703+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF4_E16_MASK;
17704+
break;
17705+
case RISCVII::LMUL_F8:
17706+
case RISCVII::LMUL_RESERVED:
17707+
llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
17708+
}
17709+
} else if (Log2SEW == 5) {
17710+
switch (LMul) {
17711+
case RISCVII::LMUL_1:
17712+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E32_MASK;
17713+
break;
17714+
case RISCVII::LMUL_2:
17715+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E32_MASK;
17716+
break;
17717+
case RISCVII::LMUL_4:
17718+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E32_MASK;
17719+
break;
17720+
case RISCVII::LMUL_8:
17721+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E32_MASK;
17722+
break;
17723+
case RISCVII::LMUL_F2:
17724+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E32_MASK;
17725+
break;
17726+
case RISCVII::LMUL_F4:
17727+
case RISCVII::LMUL_F8:
17728+
case RISCVII::LMUL_RESERVED:
17729+
llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
17730+
}
17731+
} else if (Log2SEW == 6) {
17732+
switch (LMul) {
17733+
case RISCVII::LMUL_1:
17734+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E64_MASK;
17735+
break;
17736+
case RISCVII::LMUL_2:
17737+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E64_MASK;
17738+
break;
17739+
case RISCVII::LMUL_4:
17740+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E64_MASK;
17741+
break;
17742+
case RISCVII::LMUL_8:
17743+
CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E64_MASK;
17744+
break;
17745+
case RISCVII::LMUL_F2:
17746+
case RISCVII::LMUL_F4:
17747+
case RISCVII::LMUL_F8:
17748+
case RISCVII::LMUL_RESERVED:
17749+
llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
17750+
}
17751+
} else {
17752+
llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
17753+
}
17754+
1767717755
BuildMI(*BB, MI, DL, TII.get(CVTFOpc))
1767817756
.add(MI.getOperand(0))
1767917757
.add(MI.getOperand(1))
@@ -17883,23 +17961,17 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1788317961
Subtarget);
1788417962

1788517963
case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK:
17886-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK,
17887-
RISCV::PseudoVFCVT_F_X_V_M1_MASK);
17964+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK);
1788817965
case RISCV::PseudoVFROUND_NOEXCEPT_V_M2_MASK:
17889-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK,
17890-
RISCV::PseudoVFCVT_F_X_V_M2_MASK);
17966+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK);
1789117967
case RISCV::PseudoVFROUND_NOEXCEPT_V_M4_MASK:
17892-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M4_MASK,
17893-
RISCV::PseudoVFCVT_F_X_V_M4_MASK);
17968+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M4_MASK);
1789417969
case RISCV::PseudoVFROUND_NOEXCEPT_V_M8_MASK:
17895-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M8_MASK,
17896-
RISCV::PseudoVFCVT_F_X_V_M8_MASK);
17970+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M8_MASK);
1789717971
case RISCV::PseudoVFROUND_NOEXCEPT_V_MF2_MASK:
17898-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK,
17899-
RISCV::PseudoVFCVT_F_X_V_MF2_MASK);
17972+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK);
1790017973
case RISCV::PseudoVFROUND_NOEXCEPT_V_MF4_MASK:
17901-
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK,
17902-
RISCV::PseudoVFCVT_F_X_V_MF4_MASK);
17974+
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK);
1790317975
case RISCV::PseudoFROUND_H:
1790417976
case RISCV::PseudoFROUND_H_INX:
1790517977
case RISCV::PseudoFROUND_S:

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 39 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -3580,12 +3580,14 @@ multiclass VPseudoConversion<VReg RetClass,
35803580
VReg Op1Class,
35813581
LMULInfo MInfo,
35823582
string Constraint = "",
3583+
int sew = 0,
35833584
int TargetConstraintType = 1> {
3585+
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
35843586
let VLMul = MInfo.value in {
3585-
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;
3586-
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
3587-
Constraint, TargetConstraintType>,
3588-
RISCVMaskedPseudo<MaskIdx=2>;
3587+
def suffix : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;
3588+
def suffix # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
3589+
Constraint, TargetConstraintType>,
3590+
RISCVMaskedPseudo<MaskIdx=2>;
35893591
}
35903592
}
35913593

@@ -3711,18 +3713,22 @@ multiclass VPseudoVWCVTI_RM_V {
37113713
multiclass VPseudoVWCVTF_V {
37123714
defvar constraint = "@earlyclobber $rd";
37133715
foreach m = MxListW in {
3714-
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
3715-
SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX,
3716-
forceMergeOpRead=true>;
3716+
foreach e = SchedSEWSet<m.MX, isF=0, isWidening=1>.val in
3717+
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=e,
3718+
TargetConstraintType=3>,
3719+
SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, e,
3720+
forceMergeOpRead=true>;
37173721
}
37183722
}
37193723

37203724
multiclass VPseudoVWCVTD_V {
37213725
defvar constraint = "@earlyclobber $rd";
37223726
foreach m = MxListFW in {
3723-
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
3724-
SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX,
3725-
forceMergeOpRead=true>;
3727+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3728+
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=e,
3729+
TargetConstraintType=3>,
3730+
SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, e,
3731+
forceMergeOpRead=true>;
37263732
}
37273733
}
37283734

@@ -4896,14 +4902,17 @@ multiclass VPatConversionTA<string intrinsic,
48964902
ValueType result_type,
48974903
ValueType op1_type,
48984904
ValueType mask_type,
4899-
int sew,
4905+
int log2sew,
49004906
LMULInfo vlmul,
49014907
VReg result_reg_class,
4902-
VReg op1_reg_class> {
4908+
VReg op1_reg_class,
4909+
bit isSEWAware = 0> {
49034910
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
4904-
sew, vlmul, result_reg_class, op1_reg_class>;
4911+
log2sew, vlmul, result_reg_class, op1_reg_class,
4912+
isSEWAware>;
49054913
def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type,
4906-
mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
4914+
mask_type, log2sew, vlmul, result_reg_class, op1_reg_class,
4915+
isSEWAware>;
49074916
}
49084917

49094918
multiclass VPatConversionTARoundingMode<string intrinsic,
@@ -5952,19 +5961,21 @@ multiclass VPatConversionWI_VF_RM<string intrinsic, string instruction> {
59525961
}
59535962
}
59545963

5955-
multiclass VPatConversionWF_VI<string intrinsic, string instruction> {
5964+
multiclass VPatConversionWF_VI<string intrinsic, string instruction,
5965+
bit isSEWAware = 0> {
59565966
foreach vtiToWti = AllWidenableIntToFloatVectors in {
59575967
defvar vti = vtiToWti.Vti;
59585968
defvar fwti = vtiToWti.Wti;
59595969
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
59605970
GetVTypePredicates<fwti>.Predicates) in
59615971
defm : VPatConversionTA<intrinsic, instruction, "V",
59625972
fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
5963-
vti.LMul, fwti.RegClass, vti.RegClass>;
5973+
vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
59645974
}
59655975
}
59665976

5967-
multiclass VPatConversionWF_VF<string intrinsic, string instruction> {
5977+
multiclass VPatConversionWF_VF<string intrinsic, string instruction,
5978+
bit isSEWAware = 0> {
59685979
foreach fvtiToFWti = AllWidenableFloatVectors in {
59695980
defvar fvti = fvtiToFWti.Vti;
59705981
defvar fwti = fvtiToFWti.Wti;
@@ -5974,11 +5985,12 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction> {
59745985
GetVTypePredicates<fwti>.Predicates)) in
59755986
defm : VPatConversionTA<intrinsic, instruction, "V",
59765987
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5977-
fvti.LMul, fwti.RegClass, fvti.RegClass>;
5988+
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
59785989
}
59795990
}
59805991

5981-
multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction> {
5992+
multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction,
5993+
bit isSEWAware = 0> {
59825994
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in
59835995
{
59845996
defvar fvti = fvtiToFWti.Vti;
@@ -5987,7 +5999,7 @@ multiclass VPatConversionWF_VF_BF <string intrinsic, string instruction> {
59875999
GetVTypePredicates<fwti>.Predicates) in
59886000
defm : VPatConversionTA<intrinsic, instruction, "V",
59896001
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
5990-
fvti.LMul, fwti.RegClass, fvti.RegClass>;
6002+
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
59916003
}
59926004
}
59936005

@@ -7292,11 +7304,14 @@ defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">;
72927304
defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">;
72937305
defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;
72947306
defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_x_f_v", "PseudoVFWCVT_RTZ_X_F">;
7295-
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU">;
7296-
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X">;
7297-
defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F">;
7307+
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU",
7308+
isSEWAware=1>;
7309+
defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X",
7310+
isSEWAware=1>;
7311+
defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F",
7312+
isSEWAware=1>;
72987313
defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
7299-
"PseudoVFWCVTBF16_F_F">;
7314+
"PseudoVFWCVTBF16_F_F", isSEWAware=1>;
73007315

73017316
//===----------------------------------------------------------------------===//
73027317
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,7 @@ multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop,
441441
let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,
442442
GetVTypePredicates<fwti>.Predicates) in
443443
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
444-
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
444+
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW)
445445
(fwti.Vector (IMPLICIT_DEF)),
446446
ivti.RegClass:$rs1,
447447
ivti.AVL, ivti.Log2SEW, TA_MA)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,7 +1315,7 @@ multiclass VPatWConvertI2FPVL_V<SDPatternOperator vop,
13151315
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
13161316
(ivti.Mask V0),
13171317
VLOpFrag)),
1318-
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
1318+
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW#"_MASK")
13191319
(fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
13201320
(ivti.Mask V0),
13211321
GPR:$vl, ivti.Log2SEW, TA_MA)>;
@@ -2672,7 +2672,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
26722672
(fvti.Vector fvti.RegClass:$rs1),
26732673
(fvti.Mask V0),
26742674
VLOpFrag)),
2675-
(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK")
2675+
(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
26762676
(fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
26772677
(fvti.Mask V0),
26782678
GPR:$vl, fvti.Log2SEW, TA_MA)>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -784,10 +784,11 @@ foreach mx = SchedMxListF in {
784784

785785
// Widening
786786
foreach mx = SchedMxListW in {
787-
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
788-
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
789-
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
790-
defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
787+
foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
788+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
789+
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
790+
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in
791+
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
791792
}
792793
}
793794
foreach mx = SchedMxListFW in {
@@ -801,16 +802,13 @@ foreach mx = SchedMxListFW in {
801802
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
802803
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
803804
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
805+
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
804806
}
805807
}
806-
}
807-
foreach mx = SchedMxListFW in {
808808
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
809809
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
810-
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
811-
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
812-
defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
813-
}
810+
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in
811+
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
814812
}
815813
// Narrowing
816814
foreach mx = SchedMxListW in {
@@ -1181,9 +1179,9 @@ defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
11811179
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
11821180
defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
11831181
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
1184-
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
1182+
defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
11851183
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
1186-
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1184+
defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
11871185
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
11881186
defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
11891187
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -526,19 +526,18 @@ foreach mx = SchedMxList in {
526526

527527
// Widening
528528
foreach mx = SchedMxListW in {
529-
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
530-
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;
531-
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
532-
defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFiveP600VectorArith], mx, IsWorstCase>;
529+
foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
530+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
531+
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
532+
let Latency = 3, ReleaseAtCycles = [LMulLat] in
533+
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
533534
}
534535
}
535536
foreach mx = SchedMxListFW in {
536537
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
537538
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListFW>.c;
538-
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
539-
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
540-
defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFiveP600VectorArith], mx, IsWorstCase>;
541-
}
539+
let Latency = 6, ReleaseAtCycles = [LMulLat] in
540+
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
542541
}
543542
foreach mx = SchedMxListFW in {
544543
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
@@ -551,6 +550,7 @@ foreach mx = SchedMxListFW in {
551550
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
552551
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
553552
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
553+
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
554554
}
555555
}
556556
}
@@ -962,9 +962,9 @@ defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
962962
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
963963
defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
964964
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
965-
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
965+
defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
966966
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
967-
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
967+
defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
968968
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
969969
defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
970970
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;

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