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[RISCV] Add P-ext MC support for pli.dh, pli.db, and plui.dh. (#153972)
Refactor the pli.b/h/w and plui.h/w tablegen classes.
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4 files changed

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-33
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4 files changed

+107
-33
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

Lines changed: 78 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {
2525
}
2626

2727
// A 8-bit signed immediate allowing range [-128, 255]
28-
// but represented as [-128, 127].
28+
// but represented as [-128, 255].
2929
def simm8_unsigned : RISCVOp {
3030
let ParserMatchClass = SImm8UnsignedAsmOperand;
3131
let EncoderMethod = "getImmOpValue";
@@ -62,49 +62,40 @@ def simm10_unsigned : RISCVOp {
6262
// Instruction class templates
6363
//===----------------------------------------------------------------------===//
6464

65-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
66-
class PLI_i<bits<7> funct7, string opcodestr>
67-
: RVInst<(outs GPR:$rd), (ins simm10:$imm10), opcodestr, "$rd, $imm10", [],
65+
// Common base for pli.b/h/w and plui.h/w
66+
class RVPLoadImm_i<bits<7> funct7, dag ins, string opcodestr,
67+
string argstr>
68+
: RVInst<(outs GPR:$rd), ins, opcodestr, argstr, [],
6869
InstFormatOther> {
69-
bits<10> imm10;
7070
bits<5> rd;
7171

7272
let Inst{31-25} = funct7;
73-
let Inst{24-16} = imm10{8-0};
74-
let Inst{15} = imm10{9};
7573
let Inst{14-12} = 0b010;
7674
let Inst{11-7} = rd;
7775
let Inst{6-0} = OPC_OP_IMM_32.Value;
76+
77+
let hasSideEffects = 0;
78+
let mayLoad = 0;
79+
let mayStore = 0;
7880
}
7981

80-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
81-
class PLUI_i<bits<7> funct7, string opcodestr>
82-
: RVInst<(outs GPR:$rd), (ins simm10_unsigned:$imm10), opcodestr,
83-
"$rd, $imm10", [], InstFormatOther> {
82+
// Base for pli.h/w.
83+
class PLI_i<bits<7> funct7, string opcodestr>
84+
: RVPLoadImm_i<funct7, (ins simm10:$imm10), opcodestr, "$rd, $imm10"> {
8485
bits<10> imm10;
85-
bits<5> rd;
8686

87-
let Inst{31-25} = funct7;
88-
let Inst{24} = imm10{0};
89-
let Inst{23-15} = imm10{9-1};
90-
let Inst{14-12} = 0b010;
91-
let Inst{11-7} = rd;
92-
let Inst{6-0} = OPC_OP_IMM_32.Value;
87+
let Inst{24-16} = imm10{8-0};
88+
let Inst{15} = imm10{9};
9389
}
9490

95-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
96-
class PLI_B_i<bits<8> funct8, string opcodestr>
97-
: RVInst<(outs GPR:$rd), (ins simm8_unsigned:$imm8), opcodestr,
98-
"$rd, $imm8", [], InstFormatOther> {
99-
bits<8> imm8;
100-
bits<5> rd;
91+
// Base for plui.h/w.
92+
class PLUI_i<bits<7> funct7, string opcodestr>
93+
: RVPLoadImm_i<funct7, (ins simm10_unsigned:$imm10), opcodestr,
94+
"$rd, $imm10"> {
95+
bits<10> imm10;
10196

102-
let Inst{31-24} = funct8;
103-
let Inst{23-16} = imm8;
104-
let Inst{15} = 0b0;
105-
let Inst{14-12} = 0b010;
106-
let Inst{11-7} = rd;
107-
let Inst{6-0} = OPC_OP_IMM_32.Value;
97+
let Inst{24} = imm10{0};
98+
let Inst{23-15} = imm10{9-1};
10899
}
109100

110101
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
@@ -180,14 +171,33 @@ class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
180171
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
181172
class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
182173
: RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),
183-
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
174+
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr,
175+
"$rd, $rs1, $rs2"> {
184176
let Inst{31} = 0b1;
185177
let Inst{30-27} = f;
186178
let Inst{26-25} = w;
187179

188180
let Constraints = "$rd = $rd_wb";
189181
}
190182

183+
// Common base for pli.db/h/w and plui.dh/w
184+
class RVPPairLoadImm_i<bits<7> funct7, dag ins, string opcodestr,
185+
string argstr>
186+
: RVInst<(outs GPRPairRV32:$rd), ins, opcodestr, argstr, [],
187+
InstFormatOther> {
188+
bits<5> rd;
189+
190+
let Inst{31-25} = funct7;
191+
let Inst{14-12} = 0b010;
192+
let Inst{11-8} = rd{4-1};
193+
let Inst{7} = 0b0;
194+
let Inst{6-0} = OPC_OP_IMM_32.Value;
195+
196+
let hasSideEffects = 0;
197+
let mayLoad = 0;
198+
let mayStore = 0;
199+
}
200+
191201
//===----------------------------------------------------------------------===//
192202
// Instructions
193203
//===----------------------------------------------------------------------===//
@@ -229,8 +239,16 @@ let Predicates = [HasStdExtP] in
229239
def PLI_H : PLI_i<0b1011000, "pli.h">;
230240
let Predicates = [HasStdExtP, IsRV64] in
231241
def PLI_W : PLI_i<0b1011001, "pli.w">;
232-
let Predicates = [HasStdExtP] in
233-
def PLI_B : PLI_B_i<0b10110100, "pli.b">;
242+
let Predicates = [HasStdExtP] in {
243+
def PLI_B : RVPLoadImm_i<0b1011010, (ins simm8_unsigned:$imm8), "pli.b",
244+
"$rd, $imm8"> {
245+
bits<8> imm8;
246+
247+
let Inst{24} = 0b0;
248+
let Inst{23-16} = imm8;
249+
let Inst{15} = 0b0;
250+
}
251+
}
234252

235253
let Predicates = [HasStdExtP] in {
236254
def PSEXT_H_B : RVPUnary_ri<0b00, 0b00100, "psext.h.b">;
@@ -578,3 +596,30 @@ let Predicates = [HasStdExtP, IsRV64] in {
578596
def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
579597
def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
580598
} // Predicates = [HasStdExtP, IsRV64]
599+
600+
let Predicates = [HasStdExtP, IsRV32] in {
601+
def PLI_DH : RVPPairLoadImm_i<0b0011000, (ins simm10:$imm10), "pli.dh",
602+
"$rd, $imm10"> {
603+
bits<10> imm10;
604+
605+
let Inst{24-16} = imm10{8-0};
606+
let Inst{15} = imm10{9};
607+
}
608+
609+
def PLI_DB : RVPPairLoadImm_i<0b0011010, (ins simm8_unsigned:$imm8), "pli.db",
610+
"$rd, $imm8"> {
611+
bits<8> imm8;
612+
613+
let Inst{24} = 0b0;
614+
let Inst{23-16} = imm8;
615+
let Inst{15} = 0b0;
616+
}
617+
618+
def PLUI_DH : RVPPairLoadImm_i<0b0111000, (ins simm10_unsigned:$imm10),
619+
"plui.dh", "$rd, $imm10"> {
620+
bits<10> imm10;
621+
622+
let Inst{24} = imm10{0};
623+
let Inst{23-15} = imm10{9-1};
624+
}
625+
}

‎llvm/test/MC/RISCV/rv32p-invalid.s‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,3 +106,11 @@ ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the follow
106106
ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
107107
ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
108108
ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
109+
110+
pli.dh a1, 1 # CHECK: :[[@LINE]]:8: error: register must be even
111+
pli.db s1, 1 # CHECK: :[[@LINE]]:8: error: register must be even
112+
plui.dh t2, 1 # CHECK: :[[@LINE]]:9: error: register must be even
113+
114+
pli.dh a0, 0x400 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-512, 511]
115+
pli.db a0, 0x200 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-128, 255]
116+
plui.dh a0, 0x400 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-512, 1023]

‎llvm/test/MC/RISCV/rv32p-valid.s‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,3 +376,19 @@ ppackt.h t3, s0, s0
376376
# CHECK-ASM-AND-OBJ: packt a2, t3, t1
377377
# CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb2]
378378
packt a2, t3, t1
379+
380+
# CHECK-ASM-AND-OBJ: pli.dh a4, 16
381+
# CHECK-ASM: encoding: [0x1b,0x27,0x10,0x30]
382+
pli.dh a4, 16
383+
# CHECK-ASM-AND-OBJ: pli.db a6, 16
384+
# CHECK-ASM: encoding: [0x1b,0x28,0x10,0x34]
385+
pli.db a6, 16
386+
# CHECK-ASM-AND-OBJ: pli.db a6, -128
387+
# CHECK-ASM: encoding: [0x1b,0x28,0x80,0x34]
388+
pli.db a6, -128
389+
# CHECK-ASM-AND-OBJ: plui.dh tp, 32
390+
# CHECK-ASM: encoding: [0x1b,0x22,0x08,0x70]
391+
plui.dh tp, 32
392+
# CHECK-ASM-AND-OBJ: plui.dh tp, -412
393+
# CHECK-ASM: encoding: [0x1b,0x22,0x99,0x70]
394+
plui.dh tp, 612

‎llvm/test/MC/RISCV/rv64p-invalid.s‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,3 +65,8 @@ mulsu.h00 a4, s4, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the foll
6565
maccsu.h00 s4, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
6666
mulsu.h11 s8, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
6767
maccsu.h11 s0, a2, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
68+
69+
# FIXME: This error doesn't make sense. Should say that we need RV32I.
70+
pli.dh a0, 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
71+
pli.db s0, 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
72+
plui.dh t1, 1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

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