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RKSimonRKSimon
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Add missing freeze
1 parent 08756e3 commit 60bfef2

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2 files changed

+27
-13
lines changed

2 files changed

+27
-13
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2804,19 +2804,24 @@ static Instruction *foldSelectWithClampedShift(SelectInst &SI,
28042804
Value *Amt;
28052805
if (match(CondVal, m_SpecificICmp(ICmpInst::ICMP_UGT, m_Value(Amt),
28062806
m_SpecificInt(BW - 1)))) {
2807-
if (BinaryOperator *ShiftI = MatchClampedShift(FalseVal, Amt))
2807+
if (BinaryOperator *ShiftI = MatchClampedShift(FalseVal, Amt)) {
2808+
Amt = Builder.CreateFreeze(Amt);
28082809
return SelectInst::Create(
2809-
CondVal, TrueVal,
2810+
Builder.CreateICmpUGT(Amt, cast<Instruction>(CondVal)->getOperand(1)),
2811+
TrueVal,
28102812
Builder.CreateBinOp(ShiftI->getOpcode(), ShiftI->getOperand(0), Amt));
2813+
}
28112814
}
28122815

28132816
if (match(CondVal, m_SpecificICmp(ICmpInst::ICMP_ULT, m_Value(Amt),
28142817
m_SpecificInt(BW)))) {
2815-
if (BinaryOperator *ShiftI = MatchClampedShift(TrueVal, Amt))
2818+
if (BinaryOperator *ShiftI = MatchClampedShift(TrueVal, Amt)) {
2819+
Amt = Builder.CreateFreeze(Amt);
28162820
return SelectInst::Create(
2817-
CondVal,
2821+
Builder.CreateICmpULT(Amt, cast<Instruction>(CondVal)->getOperand(1)),
28182822
Builder.CreateBinOp(ShiftI->getOpcode(), ShiftI->getOperand(0), Amt),
28192823
FalseVal);
2824+
}
28202825
}
28212826

28222827
return nullptr;

‎llvm/test/Transforms/InstCombine/select-shift-clamp.ll‎

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,9 @@ declare void @use_i32(i32)
1212

1313
define i32 @select_ult_shl_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
1414
; CHECK-LABEL: @select_ult_shl_clamp_and_i32(
15-
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
15+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
1616
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[A1]]
17+
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1]], 32
1718
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
1819
; CHECK-NEXT: ret i32 [[R]]
1920
;
@@ -26,8 +27,9 @@ define i32 @select_ult_shl_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
2627

2728
define i32 @select_ule_ashr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
2829
; CHECK-LABEL: @select_ule_ashr_clamp_and_i32(
29-
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
30+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
3031
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[A0:%.*]], [[A1]]
32+
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1]], 32
3133
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
3234
; CHECK-NEXT: ret i32 [[R]]
3335
;
@@ -40,8 +42,9 @@ define i32 @select_ule_ashr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
4042

4143
define i32 @select_ugt_lshr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
4244
; CHECK-LABEL: @select_ugt_lshr_clamp_and_i32(
43-
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
45+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
4446
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A0:%.*]], [[A1]]
47+
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1]], 31
4548
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[TMP1]]
4649
; CHECK-NEXT: ret i32 [[R]]
4750
;
@@ -54,8 +57,9 @@ define i32 @select_ugt_lshr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
5457

5558
define i32 @select_uge_shl_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
5659
; CHECK-LABEL: @select_uge_shl_clamp_and_i32(
57-
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
60+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
5861
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[A1]]
62+
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1]], 31
5963
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[TMP1]]
6064
; CHECK-NEXT: ret i32 [[R]]
6165
;
@@ -124,8 +128,9 @@ define i17 @select_uge_lshr_clamp_and_i17_nonpow2(i17 %a0, i17 %a1, i17 %a2) {
124128

125129
define i32 @select_ult_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
126130
; CHECK-LABEL: @select_ult_shl_clamp_umin_i32(
127-
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
131+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
128132
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[A1]]
133+
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1]], 32
129134
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
130135
; CHECK-NEXT: ret i32 [[R]]
131136
;
@@ -138,8 +143,9 @@ define i32 @select_ult_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
138143

139144
define i17 @select_ule_ashr_clamp_umin_i17(i17 %a0, i17 %a1, i17 %a2) {
140145
; CHECK-LABEL: @select_ule_ashr_clamp_umin_i17(
141-
; CHECK-NEXT: [[C:%.*]] = icmp ult i17 [[A1:%.*]], 17
146+
; CHECK-NEXT: [[A1:%.*]] = freeze i17 [[A3:%.*]]
142147
; CHECK-NEXT: [[TMP1:%.*]] = ashr i17 [[A0:%.*]], [[A1]]
148+
; CHECK-NEXT: [[C:%.*]] = icmp ult i17 [[A1]], 17
143149
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i17 [[TMP1]], i17 [[A2:%.*]]
144150
; CHECK-NEXT: ret i17 [[R]]
145151
;
@@ -152,8 +158,9 @@ define i17 @select_ule_ashr_clamp_umin_i17(i17 %a0, i17 %a1, i17 %a2) {
152158

153159
define i32 @select_ugt_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
154160
; CHECK-LABEL: @select_ugt_shl_clamp_umin_i32(
155-
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
161+
; CHECK-NEXT: [[A1:%.*]] = freeze i32 [[A3:%.*]]
156162
; CHECK-NEXT: [[S:%.*]] = shl i32 [[A0:%.*]], [[A1]]
163+
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1]], 31
157164
; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[S]]
158165
; CHECK-NEXT: ret i32 [[R]]
159166
;
@@ -166,8 +173,9 @@ define i32 @select_ugt_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
166173

167174
define <2 x i32> @select_uge_lshr_clamp_umin_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2) {
168175
; CHECK-LABEL: @select_uge_lshr_clamp_umin_v2i32(
169-
; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A1:%.*]], <i32 31, i32 31>
176+
; CHECK-NEXT: [[A1:%.*]] = freeze <2 x i32> [[A3:%.*]]
170177
; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[A0:%.*]], [[A1]]
178+
; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A1]], <i32 31, i32 31>
171179
; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C]], <2 x i32> [[A2:%.*]], <2 x i32> [[S]]
172180
; CHECK-NEXT: ret <2 x i32> [[R]]
173181
;
@@ -214,8 +222,9 @@ define i17 @select_uge_lshr_clamp_umin_i17_badlimit(i17 %a0, i17 %a1, i17 %a2) {
214222

215223
define range(i64 0, -9223372036854775807) <4 x i64> @PR109888(<4 x i64> %0) {
216224
; CHECK-LABEL: @PR109888(
217-
; CHECK-NEXT: [[C:%.*]] = icmp ult <4 x i64> [[TMP0:%.*]], <i64 64, i64 64, i64 64, i64 64>
225+
; CHECK-NEXT: [[TMP0:%.*]] = freeze <4 x i64> [[TMP1:%.*]]
218226
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw <4 x i64> <i64 1, i64 1, i64 1, i64 1>, [[TMP0]]
227+
; CHECK-NEXT: [[C:%.*]] = icmp ult <4 x i64> [[TMP0]], <i64 64, i64 64, i64 64, i64 64>
219228
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i64> [[TMP2]], <4 x i64> zeroinitializer
220229
; CHECK-NEXT: ret <4 x i64> [[R]]
221230
;

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