@@ -741,7 +741,7 @@ creatLdMatrixCompatibleLoads(RewriterBase &rewriter, vector::TransferReadOp op,
741741 }
742742
743743 // Adjust the load offset.
744- auto laneId = gpu::LaneIdOp::create (rewriter, loc, /* upperBound =*/ nullptr );
744+ auto laneId = gpu::LaneIdOp::create (rewriter, loc, /* upper_bound =*/ nullptr );
745745 FailureOr<AffineMap> offsets =
746746 nvgpu::getLaneIdToLdMatrixMatrixCoord (rewriter, loc, *params);
747747 if (failed (offsets)) {
@@ -781,7 +781,7 @@ createNonLdMatrixLoads(RewriterBase &rewriter, vector::TransferReadOp op,
781781 " conversion to distributed non-ldmatrix compatible load" );
782782 }
783783
784- Value laneId = gpu::LaneIdOp::create (rewriter, loc, /* upperBound =*/ nullptr );
784+ Value laneId = gpu::LaneIdOp::create (rewriter, loc, /* upper_bound =*/ nullptr );
785785
786786 // This is the individual element type.
787787 Type loadedElType = regInfo->registerLLVMType ;
@@ -915,7 +915,7 @@ convertTransferWriteToStores(RewriterBase &rewriter, vector::TransferWriteOp op,
915915 return rewriter.notifyMatchFailure (op, " not mma sync reg info" );
916916
917917 VectorType vectorType = getMmaSyncVectorOperandType (*regInfo);
918- Value laneId = gpu::LaneIdOp::create (rewriter, loc, /* upperBound =*/ nullptr );
918+ Value laneId = gpu::LaneIdOp::create (rewriter, loc, /* upper_bound =*/ nullptr );
919919
920920 for (unsigned i = 0 ; i < vectorType.getShape ()[0 ]; i++) {
921921 Value logicalValueId = arith::ConstantOp::create (
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