@@ -25,6 +25,7 @@ def rvv_vnot : PatFrag<(ops node:$in),
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(xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
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multiclass VPatUSLoadStoreSDNode<ValueType type,
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+ RegisterClass regclass,
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int log2sew,
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LMULInfo vlmul,
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OutPatFrag avl,
@@ -37,7 +38,7 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
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(load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
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log2sew, TA_MA)>;
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// Store
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- def : Pat<(store type:$rs2, (XLenVT GPR:$rs1)),
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+ def : Pat<(store ( type regclass :$rs2) , (XLenVT GPR:$rs1)),
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(store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
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}
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@@ -49,7 +50,7 @@ multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> {
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(load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL,
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m.Log2SEW, TA_MA)>;
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// Store
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- def : Pat<(store m.Mask:$rs2, GPR:$rs1),
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+ def : Pat<(store ( m.Mask VR :$rs2) , GPR:$rs1),
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(store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
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}
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@@ -884,7 +885,7 @@ multiclass VPatAVGADD_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {
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foreach vti = AllVectors in
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let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
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GetVTypePredicates<vti>.Predicates) in
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- defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
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+ defm : VPatUSLoadStoreSDNode<vti.Vector, vti.RegClass, vti. Log2SEW, vti.LMul,
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vti.AVL, vti.RegClass>;
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foreach mti = AllMasks in
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let Predicates = [HasVInstructions] in
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