Address comments

Author: V-FEXrt

llvm/test/CodeGen/DirectX/firstbithigh.ll

@@ -119,42 +119,3 @@ entry:
   %2 = call <4 x i32> @llvm.dx.firstbitshigh.v4i16(<4 x i16> %a)
   ret <4 x i32> %2
 }
-
-define noundef <4 x i32> @test_firstbituhigh_vec4_i64(<4 x i64> noundef %a)  {
-entry:
-  ; CHECK: [[ee0:%.*]] = extractelement <4 x i64> %a, i64 0
-  ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unaryBits.i64(i32 33, i64 [[ee0]])
-  ; CHECK: [[ee1:%.*]] = extractelement <4 x i64> %a, i64 1
-  ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unaryBits.i64(i32 33, i64 [[ee1]])
-  ; CHECK: [[ee2:%.*]] = extractelement <4 x i64> %a, i64 2
-  ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unaryBits.i64(i32 33, i64 [[ee2]])
-  ; CHECK: [[ee3:%.*]] = extractelement <4 x i64> %a, i64 3
-  ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unaryBits.i64(i32 33, i64 [[ee3]])
-  ; CHECK: [[rt0:%.*]] = insertelement <4 x i32> poison, i32 [[ie0]], i64 0
-  ; CHECK: [[rt1:%.*]] = insertelement <4 x i32> [[rt0]], i32 [[ie1]], i64 1
-  ; CHECK: [[rt2:%.*]] = insertelement <4 x i32> [[rt1]], i32 [[ie2]], i64 2
-  ; CHECK: [[rt3:%.*]] = insertelement <4 x i32> [[rt2]], i32 [[ie3]], i64 3
-  ; CHECK: ret <4 x i32> [[rt3]]
-  %2 = call <4 x i32> @llvm.dx.firstbituhigh.v4i64(<4 x i64> %a)
-  ret <4 x i32> %2
-}
-
-define noundef <4 x i32> @test_firstbitshigh_vec4_i64(<4 x i64> noundef %a)  {
-entry:
-  ; CHECK: [[ee0:%.*]] = extractelement <4 x i64> %a, i64 0
-  ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unaryBits.i64(i32 34, i64 [[ee0]])
-  ; CHECK: [[ee1:%.*]] = extractelement <4 x i64> %a, i64 1
-  ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unaryBits.i64(i32 34, i64 [[ee1]])
-  ; CHECK: [[ee2:%.*]] = extractelement <4 x i64> %a, i64 2
-  ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unaryBits.i64(i32 34, i64 [[ee2]])
-  ; CHECK: [[ee3:%.*]] = extractelement <4 x i64> %a, i64 3
-  ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unaryBits.i64(i32 34, i64 [[ee3]])
-  ; CHECK: [[rt0:%.*]] = insertelement <4 x i32> poison, i32 [[ie0]], i64 0
-  ; CHECK: [[rt1:%.*]] = insertelement <4 x i32> [[rt0]], i32 [[ie1]], i64 1
-  ; CHECK: [[rt2:%.*]] = insertelement <4 x i32> [[rt1]], i32 [[ie2]], i64 2
-  ; CHECK: [[rt3:%.*]] = insertelement <4 x i32> [[rt2]], i32 [[ie3]], i64 3
-  ; CHECK: ret <4 x i32> [[rt3]]
-  ; CHECK: fex
-  %2 = call <4 x i32> @llvm.dx.firstbitshigh.v4i64(<4 x i64> %a)
-  ret <4 x i32> %2
-}

llvm/test/CodeGen/DirectX/firstbitlow.ll

@@ -60,22 +60,3 @@ entry:
   %2 = call <4 x i32> @llvm.dx.firstbitlow.v4i16(<4 x i16> %a)
   ret <4 x i32> %2
 }
-
-define noundef <4 x i32> @test_firstbitlow_vec4_i64(<4 x i64> noundef %a)  {
-entry:
-  ; CHECK: [[ee0:%.*]] = extractelement <4 x i64> %a, i64 0
-  ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unaryBits.i64(i32 32, i64 [[ee0]])
-  ; CHECK: [[ee1:%.*]] = extractelement <4 x i64> %a, i64 1
-  ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unaryBits.i64(i32 32, i64 [[ee1]])
-  ; CHECK: [[ee2:%.*]] = extractelement <4 x i64> %a, i64 2
-  ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unaryBits.i64(i32 32, i64 [[ee2]])
-  ; CHECK: [[ee3:%.*]] = extractelement <4 x i64> %a, i64 3
-  ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unaryBits.i64(i32 32, i64 [[ee3]])
-  ; CHECK: [[rt0:%.*]] = insertelement <4 x i32> poison, i32 [[ie0]], i64 0
-  ; CHECK: [[rt1:%.*]] = insertelement <4 x i32> [[rt0]], i32 [[ie1]], i64 1
-  ; CHECK: [[rt2:%.*]] = insertelement <4 x i32> [[rt1]], i32 [[ie2]], i64 2
-  ; CHECK: [[rt3:%.*]] = insertelement <4 x i32> [[rt2]], i32 [[ie3]], i64 3
-  ; CHECK: ret <4 x i32> [[rt3]]
-  %2 = call <4 x i32> @llvm.dx.firstbitlow.v4i64(<4 x i64> %a)
-  ret <4 x i32> %2
-}