Remove redundant revd class and revw multiclass

Author: SpencerAbson

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -4312,8 +4312,8 @@ let Predicates = [HasSVE2p2orSME2p2] in {
   defm RBIT_ZPzZ : sve_int_perm_rev_rbit_z<"rbit">;
   defm REVB_ZPzZ : sve_int_perm_rev_revb_z<"revb">;
   defm REVH_ZPzZ : sve_int_perm_rev_revh_z<"revh">;
-  defm REVW_ZPzZ : sve_int_perm_rev_revw_z<"revw">;
-  def  REVD_ZPzZ : sve2_int_perm_revd_z<"revd">;
+  def  REVW_ZPzZ : sve_int_perm_rev_z<0b11, 0b0110, "revw", ZPR64>;
+  def  REVD_ZPzZ : sve_int_perm_rev_z<0b00, 0b1110, "revd", ZPR128>;
 } // End HasSME2p2orSVE2p2
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AArch64/SMEInstrFormats.td

@@ -1309,23 +1309,6 @@ multiclass sve2_int_perm_revd<string asm, SDPatternOperator op> {
 
 }
 
-class sve2_int_perm_revd_z<string asm>
-    : I<(outs ZPR128:$Zd), (ins PPR3bAny:$Pg, ZPR128:$Zn),
-        asm, "\t$Zd, $Pg/z, $Zn", "", []>,
-      Sched<[]> {
-  bits<5> Zd;
-  bits<3> Pg;
-  bits<5> Zn;
-  let Inst{31-24} = 0b00000101;
-  let Inst{23-22} = 0b00; // size
-  let Inst{21-13} = 0b101110101;
-  let Inst{12-10} = Pg;
-  let Inst{9-5}   = Zn;
-  let Inst{4-0}   = Zd;
-
-  let hasSideEffects = 0;
-}
-
 class sve2_clamp<string asm, bits<2> sz, bit U, ZPRRegOp zpr_ty>
     : I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm),
         asm, "\t$Zd, $Zn, $Zm", "", []>,

llvm/lib/Target/AArch64/SVEInstrFormats.td

@@ -7429,8 +7429,8 @@ multiclass sve_int_perm_rev_revw<string asm, SDPatternOperator op> {
   def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
-class sve_int_perm_rev_z<bits<2> sz8_64, bits<2> opc, string asm,
-                       ZPRRegOp zprty>
+class sve_int_perm_rev_z<bits<2> sz, bits<4> opc, string asm,
+                        ZPRRegOp zprty>
 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/z, $Zn",
   "",
@@ -7439,9 +7439,9 @@ class sve_int_perm_rev_z<bits<2> sz8_64, bits<2> opc, string asm,
   bits<3> Pg;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
-  let Inst{23-22} = sz8_64;
-  let Inst{21-18} = 0b1001;
-  let Inst{17-16} = opc;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b10;
+  let Inst{19-16} = opc;
   let Inst{15-13} = 0b101;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
@@ -7451,25 +7451,21 @@ class sve_int_perm_rev_z<bits<2> sz8_64, bits<2> opc, string asm,
 }
 
 multiclass sve_int_perm_rev_rbit_z<string asm> {
-  def _B : sve_int_perm_rev_z<0b00, 0b11, asm, ZPR8>;
-  def _H : sve_int_perm_rev_z<0b01, 0b11, asm, ZPR16>;
-  def _S : sve_int_perm_rev_z<0b10, 0b11, asm, ZPR32>;
-  def _D : sve_int_perm_rev_z<0b11, 0b11, asm, ZPR64>;
+  def _B : sve_int_perm_rev_z<0b00, 0b0111, asm, ZPR8>;
+  def _H : sve_int_perm_rev_z<0b01, 0b0111, asm, ZPR16>;
+  def _S : sve_int_perm_rev_z<0b10, 0b0111, asm, ZPR32>;
+  def _D : sve_int_perm_rev_z<0b11, 0b0111, asm, ZPR64>;
 }
 
 multiclass sve_int_perm_rev_revb_z<string asm> {
-  def _H : sve_int_perm_rev_z<0b01, 0b00, asm, ZPR16>;
-  def _S : sve_int_perm_rev_z<0b10, 0b00, asm, ZPR32>;
-  def _D : sve_int_perm_rev_z<0b11, 0b00, asm, ZPR64>;
+  def _H : sve_int_perm_rev_z<0b01, 0b0100, asm, ZPR16>;
+  def _S : sve_int_perm_rev_z<0b10, 0b0100, asm, ZPR32>;
+  def _D : sve_int_perm_rev_z<0b11, 0b0100, asm, ZPR64>;
 }
 
 multiclass sve_int_perm_rev_revh_z<string asm> {
-  def _S : sve_int_perm_rev_z<0b10, 0b01, asm, ZPR32>;
-  def _D : sve_int_perm_rev_z<0b11, 0b01, asm, ZPR64>;
-}
-
-multiclass sve_int_perm_rev_revw_z<string asm> {
-  def _D : sve_int_perm_rev_z<0b11, 0b10, asm, ZPR64>;
+  def _S : sve_int_perm_rev_z<0b10, 0b0101, asm, ZPR32>;
+  def _D : sve_int_perm_rev_z<0b11, 0b0101, asm, ZPR64>;
 }
 
 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,