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Commit 6135f14

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fix clang format
1 parent b90fd0c commit 6135f14

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3 files changed

+8
-6
lines changed

3 files changed

+8
-6
lines changed

llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -699,7 +699,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
699699
MachineIRBuilder &MIRBuilder,
700700
SPIRVGlobalRegistry *GR) {
701701
if (Call->isSpirvOp())
702-
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
702+
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
703+
Register(0));
703704

704705
Register ScopeRegister =
705706
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2679,13 +2680,13 @@ static bool generateConvertInst(const StringRef DemangledCall,
26792680
}
26802681
} else if (GR->isScalarOrVectorOfType(Call->ReturnRegister,
26812682
SPIRV::OpTypeFloat)) {
2682-
if(Builtin->IsTF32){
2683+
if (Builtin->IsTF32) {
26832684
const auto *ST = static_cast<const SPIRVSubtarget *>(
2684-
&MIRBuilder.getMF().getSubtarget());
2685+
&MIRBuilder.getMF().getSubtarget());
26852686
if (!ST->canUseExtension(
26862687
SPIRV::Extension::SPV_INTEL_tensor_float32_conversion))
26872688
NeedExtMsg = "SPV_INTEL_tensor_float32_conversion";
2688-
IsRightComponentsNumber =
2689+
IsRightComponentsNumber =
26892690
GR->getScalarOrVectorComponentCount(Call->Arguments[0]) ==
26902691
GR->getScalarOrVectorComponentCount(Call->ReturnRegister);
26912692
Opcode = SPIRV::OpRoundFToTF32INTEL;

llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
103103
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
104104
{"SPV_KHR_float_controls2",
105105
SPIRV::Extension::Extension::SPV_KHR_float_controls2},
106-
{"SPV_INTEL_tensor_float32_conversion",
106+
{"SPV_INTEL_tensor_float32_conversion",
107107
SPIRV::Extension::Extension::SPV_INTEL_tensor_float32_conversion}};
108108

109109
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1565,7 +1565,8 @@ void addInstrRequirements(const MachineInstr &MI,
15651565
}
15661566
break;
15671567
case SPIRV::OpRoundFToTF32INTEL:
1568-
if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_tensor_float32_conversion)) {
1568+
if (ST.canUseExtension(
1569+
SPIRV::Extension::SPV_INTEL_tensor_float32_conversion)) {
15691570
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_tensor_float32_conversion);
15701571
Reqs.addCapability(SPIRV::Capability::TensorFloat32RoundingINTEL);
15711572
}

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