Removed the legalization of the Opcode and used lower()

Author: SubashBoopathi

llvm/include/llvm/Support/TargetOpcodes.def

@@ -643,7 +643,7 @@ HANDLE_TARGET_OPCODE(G_FMA)
 
 /// Generic FP multiply and add. Behaves as separate fmul and fadd.
 HANDLE_TARGET_OPCODE(G_FMAD)
-HANDLE_TARGET_OPCODE(G_STRICT_FMULADD)
+HANDLE_TARGET_OPCODE(G_STRICT_FMAD)
 
 /// Generic FP division.
 HANDLE_TARGET_OPCODE(G_FDIV)

llvm/include/llvm/Target/GenericOpcodes.td

@@ -1716,7 +1716,7 @@ def G_STRICT_FREM : ConstrainedInstruction<G_FREM>;
 def G_STRICT_FMA : ConstrainedInstruction<G_FMA>;
 def G_STRICT_FSQRT : ConstrainedInstruction<G_FSQRT>;
 def G_STRICT_FLDEXP : ConstrainedInstruction<G_FLDEXP>;
-def G_STRICT_FMULADD : ConstrainedInstruction<G_FMAD>;
+def G_STRICT_FMAD : ConstrainedInstruction<G_FMAD>;
 
 //------------------------------------------------------------------------------
 // Memory intrinsics

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

@@ -2081,7 +2081,7 @@ static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
   case Intrinsic::experimental_constrained_ldexp:
     return TargetOpcode::G_STRICT_FLDEXP;
   case Intrinsic::experimental_constrained_fmuladd:
-    return TargetOpcode::G_STRICT_FMULADD;
+    return TargetOpcode::G_STRICT_FMAD;
   default:
     return 0;
   }

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -4523,6 +4523,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
     return Legalized;
   }
   case TargetOpcode::G_FMAD:
+  case TargetOpcode::G_STRICT_FMAD:
     return lowerFMad(MI);
   case TargetOpcode::G_FFLOOR:
     return lowerFFloor(MI);

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -232,9 +232,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
   bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
                  bool IsSigned) const;
 
-  bool selectStrictFMulAdd(Register ResVReg, const SPIRVType *ResType,
-                           MachineInstr &I) const;
-
   bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
 
@@ -716,9 +713,6 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
   case TargetOpcode::G_FMA:
     return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
 
-  case TargetOpcode::G_STRICT_FMULADD:
-    return selectStrictFMulAdd(ResVReg, ResType, I);
-
   case TargetOpcode::G_STRICT_FLDEXP:
     return selectExtInst(ResVReg, ResType, I, CL::ldexp);
 
@@ -1068,37 +1062,6 @@ bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
   return MIB.constrainAllUses(TII, TRI, RBI);
 }
 
-bool SPIRVInstructionSelector::selectStrictFMulAdd(Register ResVReg,
-                                                   const SPIRVType *ResType,
-                                                   MachineInstr &I) const {
-  MachineBasicBlock &BB = *I.getParent();
-  Register MulLHS = I.getOperand(1).getReg();
-  Register MulRHS = I.getOperand(2).getReg();
-  Register AddRHS = I.getOperand(3).getReg();
-  SPIRVType *MulLHSType = GR.getSPIRVTypeForVReg(MulLHS);
-  unsigned MulOpcode, AddOpcode;
-  if (MulLHSType->getOpcode() == SPIRV::OpTypeFloat) {
-    MulOpcode = SPIRV::OpFMulS;
-    AddOpcode = SPIRV::OpFAddS;
-  } else {
-    MulOpcode = SPIRV::OpFMulV;
-    AddOpcode = SPIRV::OpFAddV;
-  }
-  Register MulTemp = MRI->createVirtualRegister(MRI->getRegClass(MulLHS));
-  BuildMI(BB, I, I.getDebugLoc(), TII.get(MulOpcode))
-      .addDef(MulTemp)
-      .addUse(GR.getSPIRVTypeID(ResType))
-      .addUse(MulLHS)
-      .addUse(MulRHS)
-      .constrainAllUses(TII, TRI, RBI);
-  return BuildMI(BB, I, I.getDebugLoc(), TII.get(AddOpcode))
-      .addDef(ResVReg)
-      .addUse(GR.getSPIRVTypeID(ResType))
-      .addUse(MulTemp)
-      .addUse(AddRHS)
-      .constrainAllUses(TII, TRI, RBI);
-}
-
 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
                                           const SPIRVType *ResType,
                                           MachineInstr &I,

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

@@ -193,9 +193,12 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
       .legalFor(allIntScalarsAndVectors)
       .legalIf(extendedScalarsAndVectors);
 
-  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA, G_STRICT_FMULADD})
+  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA})
       .legalFor(allFloatScalarsAndVectors);
 
+  getActionDefinitionsBuilder(G_STRICT_FMAD)
+      .lower();
+
   getActionDefinitionsBuilder(G_STRICT_FLDEXP)
       .legalForCartesianProduct(allFloatScalarsAndVectors, allIntScalars);