fixup! override rd in fillMemoryOperands

Author: sunshaoce

llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s

@@ -53,5 +53,5 @@ C_LDSP:      ---
 C_LDSP-NEXT: mode: latency
 C_LDSP-NEXT: key:
 C_LDSP-NEXT:   instructions:
-C_LDSP-NEXT:     - 'C_LDSP [[REG111:X[0-9]+]] X2 [[IMM11:i_0x[0-9]+]]'
+C_LDSP-NEXT:     - 'C_LDSP X2 X2 [[IMM11:i_0x[0-9]+]]'
 C_LDSP-DAG: ...

llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp

@@ -823,6 +823,7 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
   if (Opcode == RISCV::C_LDSP || Opcode == RISCV::C_LWSP ||
       Opcode == RISCV::C_SDSP || Opcode == RISCV::C_SWSP) {
     // Force base register to SP (X2)
+    IT.getValueFor(I.Operands[0]) = MCOperand::createReg(RISCV::X2);
     IT.getValueFor(MemOp) = MCOperand::createReg(RISCV::X2);
     return;
   }

llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp

@@ -142,7 +142,12 @@ static void appendCodeTemplates(const LLVMState &State,
         return;
 
       ET.fillMemoryOperands(Variant, ScratchMemoryRegister, 0);
-      Variant.getValueFor(DefOp) = MCOperand::createReg(ScratchMemoryRegister);
+
+      // Only force the def register to ScratchMemoryRegister if the target
+      // hasn't assigned a value yet.
+      MCOperand &DefVal = Variant.getValueFor(DefOp);
+      if (!DefVal.isValid())
+        DefVal = MCOperand::createReg(ScratchMemoryRegister);
 
       CodeTemplate CT;
       CT.Execution = ExecutionModeBit;