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‎llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefix=CHECK-128
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s | FileCheck %s --check-prefix=CHECK-256
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-max=512 < %s | FileCheck %s --check-prefix=CHECK-512
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=1024 -aarch64-sve-vector-bits-max=1024 < %s | FileCheck %s --check-prefix=CHECK-1024
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=2048 -aarch64-sve-vector-bits-max=2048 < %s | FileCheck %s --check-prefix=CHECK-2048
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define void @nxv16i8(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: mov w8, #256 // =0x100
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-NEXT: ret
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;
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; CHECK-128-LABEL: nxv16i8:
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; CHECK-128: // %bb.0:
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; CHECK-128-NEXT: ptrue p0.b
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; CHECK-128-NEXT: mov w8, #256 // =0x100
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; CHECK-128-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-128-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-128-NEXT: ret
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;
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; CHECK-256-LABEL: nxv16i8:
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; CHECK-256: // %bb.0:
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; CHECK-256-NEXT: ptrue p0.b
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; CHECK-256-NEXT: mov w8, #256 // =0x100
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; CHECK-256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-256-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-256-NEXT: ret
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;
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; CHECK-512-LABEL: nxv16i8:
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; CHECK-512: // %bb.0:
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; CHECK-512-NEXT: ptrue p0.b
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; CHECK-512-NEXT: mov w8, #256 // =0x100
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; CHECK-512-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-512-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-512-NEXT: ret
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;
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; CHECK-1024-LABEL: nxv16i8:
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; CHECK-1024: // %bb.0:
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; CHECK-1024-NEXT: ptrue p0.b
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; CHECK-1024-NEXT: mov w8, #256 // =0x100
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; CHECK-1024-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-1024-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-1024-NEXT: ret
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;
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; CHECK-2048-LABEL: nxv16i8:
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; CHECK-2048: // %bb.0:
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; CHECK-2048-NEXT: ptrue p0.b
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; CHECK-2048-NEXT: mov w8, #256 // =0x100
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; CHECK-2048-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; CHECK-2048-NEXT: st1b { z0.b }, p0, [x1, x8]
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; CHECK-2048-NEXT: ret
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%ldoff = getelementptr inbounds nuw i8, ptr %ldptr, i64 256
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%stoff = getelementptr inbounds nuw i8, ptr %stptr, i64 256
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%x = load <vscale x 16 x i8>, ptr %ldoff, align 1
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store <vscale x 16 x i8> %x, ptr %stoff, align 1
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ret void
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}
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define void @nxv8i16(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: mov x8, #128 // =0x80
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-NEXT: ret
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;
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; CHECK-128-LABEL: nxv8i16:
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; CHECK-128: // %bb.0:
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; CHECK-128-NEXT: ptrue p0.h
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; CHECK-128-NEXT: mov x8, #128 // =0x80
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; CHECK-128-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-128-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-128-NEXT: ret
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;
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; CHECK-256-LABEL: nxv8i16:
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; CHECK-256: // %bb.0:
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; CHECK-256-NEXT: ptrue p0.h
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; CHECK-256-NEXT: mov x8, #128 // =0x80
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; CHECK-256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-256-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-256-NEXT: ret
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;
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; CHECK-512-LABEL: nxv8i16:
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; CHECK-512: // %bb.0:
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; CHECK-512-NEXT: ptrue p0.h
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; CHECK-512-NEXT: mov x8, #128 // =0x80
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; CHECK-512-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-512-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-512-NEXT: ret
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;
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; CHECK-1024-LABEL: nxv8i16:
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; CHECK-1024: // %bb.0:
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; CHECK-1024-NEXT: ptrue p0.h
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; CHECK-1024-NEXT: mov x8, #128 // =0x80
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; CHECK-1024-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-1024-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-1024-NEXT: ret
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;
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; CHECK-2048-LABEL: nxv8i16:
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; CHECK-2048: // %bb.0:
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; CHECK-2048-NEXT: ptrue p0.h
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; CHECK-2048-NEXT: mov x8, #128 // =0x80
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; CHECK-2048-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; CHECK-2048-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; CHECK-2048-NEXT: ret
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%ldoff = getelementptr inbounds nuw i16, ptr %ldptr, i64 128
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%stoff = getelementptr inbounds nuw i16, ptr %stptr, i64 128
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%x = load <vscale x 8 x i16>, ptr %ldoff, align 2
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store <vscale x 8 x i16> %x, ptr %stoff, align 2
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ret void
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}
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define void @nxv4i32(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov x8, #64 // =0x40
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-NEXT: ret
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;
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; CHECK-128-LABEL: nxv4i32:
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; CHECK-128: // %bb.0:
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; CHECK-128-NEXT: ptrue p0.s
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; CHECK-128-NEXT: mov x8, #64 // =0x40
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; CHECK-128-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-128-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-128-NEXT: ret
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;
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; CHECK-256-LABEL: nxv4i32:
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; CHECK-256: // %bb.0:
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; CHECK-256-NEXT: ptrue p0.s
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; CHECK-256-NEXT: mov x8, #64 // =0x40
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; CHECK-256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-256-NEXT: ret
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;
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; CHECK-512-LABEL: nxv4i32:
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; CHECK-512: // %bb.0:
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; CHECK-512-NEXT: ptrue p0.s
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; CHECK-512-NEXT: mov x8, #64 // =0x40
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; CHECK-512-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-512-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-512-NEXT: ret
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;
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; CHECK-1024-LABEL: nxv4i32:
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; CHECK-1024: // %bb.0:
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; CHECK-1024-NEXT: ptrue p0.s
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; CHECK-1024-NEXT: mov x8, #64 // =0x40
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; CHECK-1024-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-1024-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-1024-NEXT: ret
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;
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; CHECK-2048-LABEL: nxv4i32:
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; CHECK-2048: // %bb.0:
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; CHECK-2048-NEXT: ptrue p0.s
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; CHECK-2048-NEXT: mov x8, #64 // =0x40
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; CHECK-2048-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-2048-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; CHECK-2048-NEXT: ret
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%ldoff = getelementptr inbounds nuw i32, ptr %ldptr, i64 64
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%stoff = getelementptr inbounds nuw i32, ptr %stptr, i64 64
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%x = load <vscale x 4 x i32>, ptr %ldoff, align 4
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store <vscale x 4 x i32> %x, ptr %stoff, align 4
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ret void
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}
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define void @nxv2i64(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x8, #32 // =0x20
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-NEXT: ret
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;
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; CHECK-128-LABEL: nxv2i64:
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; CHECK-128: // %bb.0:
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; CHECK-128-NEXT: ptrue p0.d
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; CHECK-128-NEXT: mov x8, #32 // =0x20
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; CHECK-128-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-128-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-128-NEXT: ret
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;
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; CHECK-256-LABEL: nxv2i64:
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; CHECK-256: // %bb.0:
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; CHECK-256-NEXT: ptrue p0.d
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; CHECK-256-NEXT: mov x8, #32 // =0x20
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; CHECK-256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-256-NEXT: ret
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;
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; CHECK-512-LABEL: nxv2i64:
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; CHECK-512: // %bb.0:
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; CHECK-512-NEXT: ptrue p0.d
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; CHECK-512-NEXT: mov x8, #32 // =0x20
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; CHECK-512-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-512-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-512-NEXT: ret
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;
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; CHECK-1024-LABEL: nxv2i64:
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; CHECK-1024: // %bb.0:
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; CHECK-1024-NEXT: ptrue p0.d
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; CHECK-1024-NEXT: mov x8, #32 // =0x20
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; CHECK-1024-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-1024-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-1024-NEXT: ret
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;
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; CHECK-2048-LABEL: nxv2i64:
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; CHECK-2048: // %bb.0:
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; CHECK-2048-NEXT: ptrue p0.d
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; CHECK-2048-NEXT: mov x8, #32 // =0x20
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; CHECK-2048-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; CHECK-2048-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; CHECK-2048-NEXT: ret
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%ldoff = getelementptr inbounds nuw i64, ptr %ldptr, i64 32
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%stoff = getelementptr inbounds nuw i64, ptr %stptr, i64 32
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%x = load <vscale x 2 x i64>, ptr %ldoff, align 8
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store <vscale x 2 x i64> %x, ptr %stoff, align 8
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ret void
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}

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