Skip to content

Commit 62735d2

Browse files
authored
[DAGCombine] Correctly extend the constant RHS in TargetLowering::SimplifySetCC (#152862)
In #150270, when the predicate is eq/ne and the trunc has only an nsw flag, the RHS is incorrectly zero-extended. Closes #152630.
1 parent 24b7727 commit 62735d2

File tree

2 files changed

+39
-4
lines changed

2 files changed

+39
-4
lines changed

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5125,10 +5125,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51255125
!ISD::isUnsignedIntSetCC(Cond))) &&
51265126
isTypeDesirableForOp(ISD::SETCC, N0.getOperand(0).getValueType())) {
51275127
EVT NewVT = N0.getOperand(0).getValueType();
5128-
SDValue NewConst = DAG.getConstant(ISD::isSignedIntSetCC(Cond)
5129-
? C1.sext(NewVT.getSizeInBits())
5130-
: C1.zext(NewVT.getSizeInBits()),
5131-
dl, NewVT);
5128+
SDValue NewConst = DAG.getConstant(
5129+
(N0->getFlags().hasNoSignedWrap() && !ISD::isUnsignedIntSetCC(Cond))
5130+
? C1.sext(NewVT.getSizeInBits())
5131+
: C1.zext(NewVT.getSizeInBits()),
5132+
dl, NewVT);
51325133
return DAG.getSetCC(dl, VT, N0.getOperand(0), NewConst, Cond);
51335134
}
51345135

llvm/test/CodeGen/X86/pr152630.ll

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
3+
4+
define i32 @pr152630(i1 %cond) nounwind {
5+
; CHECK-LABEL: pr152630:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: andl $1, %edi
8+
; CHECK-NEXT: decl %edi
9+
; CHECK-NEXT: cmpl $-1, %edi
10+
; CHECK-NEXT: je .LBB0_2
11+
; CHECK-NEXT: # %bb.1: # %entry
12+
; CHECK-NEXT: movzbl %dil, %eax
13+
; CHECK-NEXT: testl %eax, %eax
14+
; CHECK-NEXT: jne .LBB0_3
15+
; CHECK-NEXT: .LBB0_2: # %if.then
16+
; CHECK-NEXT: xorl %eax, %eax
17+
; CHECK-NEXT: retq
18+
; CHECK-NEXT: .LBB0_3: # %if.else
19+
; CHECK-NEXT: movl $1, %eax
20+
; CHECK-NEXT: retq
21+
entry:
22+
%sel = select i1 %cond, i32 0, i32 -1
23+
%conv = trunc nsw i32 %sel to i8
24+
switch i8 %conv, label %if.else [
25+
i8 -1, label %if.then
26+
i8 0, label %if.then
27+
]
28+
29+
if.then:
30+
ret i32 0
31+
32+
if.else:
33+
ret i32 1
34+
}

0 commit comments

Comments
 (0)