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[InstCombine] Add more tests. NFC.
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llvm/test/Transforms/InstCombine/icmp-dom.ll

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@@ -733,4 +733,82 @@ entry:
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ret i1 %cmp
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}
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; TODO: We can prove `%cond2` is always false
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define void @test_nonequal_domcond_loop1(i32 %x0, i1 %x1) {
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; CHECK-LABEL: @test_nonequal_domcond_loop1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[X0:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: br label [[LATCH]]
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; CHECK: latch:
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; CHECK-NEXT: br i1 [[X1:%.*]], label [[IF_THEN:%.*]], label [[LOOP_HEADER]]
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; CHECK: if.then:
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X0]], 1
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; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32 [[AND]], [[PHI]]
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; CHECK-NEXT: br i1 [[COND1]], label [[IF_THEN2:%.*]], label [[LATCH]]
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; CHECK: if.then2:
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: indirectbb:
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; CHECK-NEXT: [[COND2:%.*]] = icmp eq i32 [[PHI]], 31
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; CHECK-NEXT: br i1 [[COND2]], label [[EXIT:%.*]], label [[LATCH]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%phi = phi i32 [ 0, %entry ], [ %x0, %latch ]
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br label %latch
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latch:
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br i1 %x1, label %if.then, label %loop.header
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if.then:
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%and = and i32 %x0, 1
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%cond1 = icmp eq i32 %and, %phi
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br i1 %cond1, label %if.then2, label %latch
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if.then2:
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br label %indirectbb
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indirectbb:
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%cond2 = icmp eq i32 %phi, 31
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br i1 %cond2, label %exit, label %latch
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exit:
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ret void
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}
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define void @test_nonequal_domcond_loop2(ptr %p) {
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; CHECK-LABEL: @test_nonequal_domcond_loop2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOAD1:%.*]] = load volatile i8, ptr [[P:%.*]], align 1
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[LOAD2:%.*]] = load volatile i8, ptr [[P]], align 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LOAD2]], 0
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; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i8 [[LOAD2]], [[LOAD1]]
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; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
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; CHECK-NEXT: br i1 [[OR]], label [[WHILE_COND]], label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: br i1 false, label [[WHILE_COND]], label [[FOR_BODY]]
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;
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entry:
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%load1 = load volatile i8, ptr %p, align 1
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br label %while.cond
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while.cond:
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%load2 = load volatile i8, ptr %p, align 1
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%cmp1 = icmp eq i8 %load2, 0
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%cmp2 = icmp uge i8 %load2, %load1
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%or = select i1 %cmp1, i1 true, i1 %cmp2
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br i1 %or, label %while.cond, label %for.body
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for.body:
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%cond = icmp eq i8 %load1, %load2
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br i1 %cond, label %while.cond, label %for.body
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}
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declare void @side_effect()

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