@@ -733,4 +733,82 @@ entry:
733733 ret i1 %cmp
734734}
735735
736+ ; TODO: We can prove `%cond2` is always false
737+ define void @test_nonequal_domcond_loop1 (i32 %x0 , i1 %x1 ) {
738+ ; CHECK-LABEL: @test_nonequal_domcond_loop1(
739+ ; CHECK-NEXT: entry:
740+ ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
741+ ; CHECK: loop.header:
742+ ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[X0:%.*]], [[LATCH:%.*]] ]
743+ ; CHECK-NEXT: br label [[LATCH]]
744+ ; CHECK: latch:
745+ ; CHECK-NEXT: br i1 [[X1:%.*]], label [[IF_THEN:%.*]], label [[LOOP_HEADER]]
746+ ; CHECK: if.then:
747+ ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X0]], 1
748+ ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32 [[AND]], [[PHI]]
749+ ; CHECK-NEXT: br i1 [[COND1]], label [[IF_THEN2:%.*]], label [[LATCH]]
750+ ; CHECK: if.then2:
751+ ; CHECK-NEXT: br label [[BB:%.*]]
752+ ; CHECK: indirectbb:
753+ ; CHECK-NEXT: [[COND2:%.*]] = icmp eq i32 [[PHI]], 31
754+ ; CHECK-NEXT: br i1 [[COND2]], label [[EXIT:%.*]], label [[LATCH]]
755+ ; CHECK: exit:
756+ ; CHECK-NEXT: ret void
757+ ;
758+ entry:
759+ br label %loop.header
760+
761+ loop.header:
762+ %phi = phi i32 [ 0 , %entry ], [ %x0 , %latch ]
763+ br label %latch
764+
765+ latch:
766+ br i1 %x1 , label %if.then , label %loop.header
767+
768+ if.then:
769+ %and = and i32 %x0 , 1
770+ %cond1 = icmp eq i32 %and , %phi
771+ br i1 %cond1 , label %if.then2 , label %latch
772+
773+ if.then2:
774+ br label %indirectbb
775+
776+ indirectbb:
777+ %cond2 = icmp eq i32 %phi , 31
778+ br i1 %cond2 , label %exit , label %latch
779+
780+ exit:
781+ ret void
782+ }
783+
784+ define void @test_nonequal_domcond_loop2 (ptr %p ) {
785+ ; CHECK-LABEL: @test_nonequal_domcond_loop2(
786+ ; CHECK-NEXT: entry:
787+ ; CHECK-NEXT: [[LOAD1:%.*]] = load volatile i8, ptr [[P:%.*]], align 1
788+ ; CHECK-NEXT: br label [[WHILE_COND:%.*]]
789+ ; CHECK: while.cond:
790+ ; CHECK-NEXT: [[LOAD2:%.*]] = load volatile i8, ptr [[P]], align 1
791+ ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[LOAD2]], 0
792+ ; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i8 [[LOAD2]], [[LOAD1]]
793+ ; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
794+ ; CHECK-NEXT: br i1 [[OR]], label [[WHILE_COND]], label [[FOR_BODY:%.*]]
795+ ; CHECK: for.body:
796+ ; CHECK-NEXT: br i1 false, label [[WHILE_COND]], label [[FOR_BODY]]
797+ ;
798+ entry:
799+ %load1 = load volatile i8 , ptr %p , align 1
800+ br label %while.cond
801+
802+ while.cond:
803+ %load2 = load volatile i8 , ptr %p , align 1
804+ %cmp1 = icmp eq i8 %load2 , 0
805+ %cmp2 = icmp uge i8 %load2 , %load1
806+ %or = select i1 %cmp1 , i1 true , i1 %cmp2
807+ br i1 %or , label %while.cond , label %for.body
808+
809+ for.body:
810+ %cond = icmp eq i8 %load1 , %load2
811+ br i1 %cond , label %while.cond , label %for.body
812+ }
813+
736814declare void @side_effect ()
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