Regen test

Author: piotrAMD

llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll

@@ -1,48 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
 
-; CHECK-LABEL: {{^}}signal_unknown_wgs:
-; CHECK: s_barrier_signal
 define amdgpu_kernel void @signal_unknown_wgs() {
+; CHECK-LABEL: signal_unknown_wgs:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_barrier_signal -1
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
   ret void
 }
 
-; CHECK-LABEL: {{^}}signal_flat_wgs_attr_32_128:
-; CHECK: s_barrier_signal
 define amdgpu_kernel void @signal_flat_wgs_attr_32_128() #1 {
+; CHECK-LABEL: signal_flat_wgs_attr_32_128:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_barrier_signal -1
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
   ret void
 }
 
-; CHECK-LABEL: {{^}}signal_flat_wgs_attr_16_32:
-; CHECK: :
-; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @signal_flat_wgs_attr_16_32() #2 {
+; CHECK-LABEL: signal_flat_wgs_attr_16_32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.signal(i32 -1)
   ret void
 }
 
 
-; CHECK-LABEL: {{^}}wait_unknown_wgs:
-; CHECK: s_barrier_wait
 define amdgpu_kernel void @wait_unknown_wgs() {
+; CHECK-LABEL: wait_unknown_wgs:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_barrier_wait -1
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
   ret void
 }
 
-; CHECK-LABEL: {{^}}wait_flat_wgs_attr_32_128:
-; CHECK: s_barrier_wait
 define amdgpu_kernel void @wait_flat_wgs_attr_32_128() #1 {
+; CHECK-LABEL: wait_flat_wgs_attr_32_128:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_barrier_wait -1
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
   ret void
 }
 
-; CHECK-LABEL: {{^}}wait_flat_wgs_attr_16_32:
-; CHECK: :
-; CHECK-NEXT: ; wave barrier
-; CHECK-NEXT: s_endpgm
 define amdgpu_kernel void @wait_flat_wgs_attr_16_32() #2 {
+; CHECK-LABEL: wait_flat_wgs_attr_16_32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    ; wave barrier
+; CHECK-NEXT:    s_endpgm
   tail call void @llvm.amdgcn.s.barrier.wait(i16 -1)
   ret void
 }