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[LoongArch] Add patterns to support vector type average instructions generation
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‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td‎

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Original file line numberDiff line numberDiff line change
@@ -2024,6 +2024,56 @@ def : Pat<(v4i32(fp_to_uint v4f64:$vj)),
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(XVFTINTRZ_LU_D v4f64:$vj)),
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sub_128)>;
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// XVAVG_{B/H/W/D/BU/HU/WU/DU}, XVAVGR_{B/H/W/D/BU/HU/WU/DU}
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def : Pat<(sra (v32i8 (add v32i8:$xj, v32i8:$xk)), (v32i8 (vsplat_imm_eq_1))),
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(XVAVG_B v32i8:$xj, v32i8:$xk)>;
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def : Pat<(sra (v16i16 (add v16i16:$xj, v16i16:$xk)), (v16i16 (vsplat_imm_eq_1))),
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(XVAVG_H v16i16:$xj, v16i16:$xk)>;
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def : Pat<(sra (v8i32 (add v8i32:$xj, v8i32:$xk)), (v8i32 (vsplat_imm_eq_1))),
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(XVAVG_W v8i32:$xj, v8i32:$xk)>;
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def : Pat<(sra (v4i64 (add v4i64:$xj, v4i64:$xk)), (v4i64 (vsplat_imm_eq_1))),
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(XVAVG_D v4i64:$xj, v4i64:$xk)>;
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def : Pat<(srl (v32i8 (add v32i8:$xj, v32i8:$xk)), (v32i8 (vsplat_imm_eq_1))),
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(XVAVG_BU v32i8:$xj, v32i8:$xk)>;
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def : Pat<(srl (v16i16 (add v16i16:$xj, v16i16:$xk)), (v16i16 (vsplat_imm_eq_1))),
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(XVAVG_HU v16i16:$xj, v16i16:$xk)>;
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def : Pat<(srl (v8i32 (add v8i32:$xj, v8i32:$xk)), (v8i32 (vsplat_imm_eq_1))),
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(XVAVG_WU v8i32:$xj, v8i32:$xk)>;
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def : Pat<(srl (v4i64 (add v4i64:$xj, v4i64:$xk)), (v4i64 (vsplat_imm_eq_1))),
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(XVAVG_DU v4i64:$xj, v4i64:$xk)>;
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def : Pat<(sra (v32i8 (add (v32i8 (add v32i8:$vj, v32i8:$vk)),
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(v32i8 (vsplat_imm_eq_1)))),
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(v32i8 (vsplat_imm_eq_1))),
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(XVAVGR_B v32i8:$vj, v32i8:$vk)>;
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def : Pat<(sra (v16i16 (add (v16i16 (add v16i16:$vj, v16i16:$vk)),
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(v16i16 (vsplat_imm_eq_1)))),
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(v16i16 (vsplat_imm_eq_1))),
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(XVAVGR_H v16i16:$vj, v16i16:$vk)>;
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def : Pat<(sra (v8i32 (add (v8i32 (add v8i32:$vj, v8i32:$vk)),
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(v8i32 (vsplat_imm_eq_1)))),
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(v8i32 (vsplat_imm_eq_1))),
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(XVAVGR_W v8i32:$vj, v8i32:$vk)>;
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def : Pat<(sra (v4i64 (add (v4i64 (add v4i64:$vj, v4i64:$vk)),
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(v4i64 (vsplat_imm_eq_1)))),
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(v4i64 (vsplat_imm_eq_1))),
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(XVAVGR_D v4i64:$vj, v4i64:$vk)>;
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def : Pat<(srl (v32i8 (add (v32i8 (add v32i8:$vj, v32i8:$vk)),
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(v32i8 (vsplat_imm_eq_1)))),
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(v32i8 (vsplat_imm_eq_1))),
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(XVAVGR_BU v32i8:$vj, v32i8:$vk)>;
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def : Pat<(srl (v16i16 (add (v16i16 (add v16i16:$vj, v16i16:$vk)),
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(v16i16 (vsplat_imm_eq_1)))),
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(v16i16 (vsplat_imm_eq_1))),
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(XVAVGR_HU v16i16:$vj, v16i16:$vk)>;
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def : Pat<(srl (v8i32 (add (v8i32 (add v8i32:$vj, v8i32:$vk)),
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(v8i32 (vsplat_imm_eq_1)))),
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(v8i32 (vsplat_imm_eq_1))),
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(XVAVGR_WU v8i32:$vj, v8i32:$vk)>;
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def : Pat<(srl (v4i64 (add (v4i64 (add v4i64:$vj, v4i64:$vk)),
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(v4i64 (vsplat_imm_eq_1)))),
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(v4i64 (vsplat_imm_eq_1))),
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(XVAVGR_DU v4i64:$vj, v4i64:$vk)>;
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// abs
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def : Pat<(abs v32i8:$xj), (XVSIGNCOV_B v32i8:$xj, v32i8:$xj)>;
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def : Pat<(abs v16i16:$xj), (XVSIGNCOV_H v16i16:$xj, v16i16:$xj)>;

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2154,6 +2154,56 @@ def : Pat<(f32 f32imm_vldi:$in),
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def : Pat<(f64 f64imm_vldi:$in),
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(f64 (EXTRACT_SUBREG (VLDI (to_f64imm_vldi f64imm_vldi:$in)), sub_64))>;
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// VAVG_{B/H/W/D/BU/HU/WU/DU}, VAVGR_{B/H/W/D/BU/HU/WU/DU}
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def : Pat<(sra (v16i8 (add v16i8:$vj, v16i8:$vk)), (v16i8 (vsplat_imm_eq_1))),
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(VAVG_B v16i8:$vj, v16i8:$vk)>;
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def : Pat<(sra (v8i16 (add v8i16:$vj, v8i16:$vk)), (v8i16 (vsplat_imm_eq_1))),
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(VAVG_H v8i16:$vj, v8i16:$vk)>;
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def : Pat<(sra (v4i32 (add v4i32:$vj, v4i32:$vk)), (v4i32 (vsplat_imm_eq_1))),
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(VAVG_W v4i32:$vj, v4i32:$vk)>;
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def : Pat<(sra (v2i64 (add v2i64:$vj, v2i64:$vk)), (v2i64 (vsplat_imm_eq_1))),
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(VAVG_D v2i64:$vj, v2i64:$vk)>;
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def : Pat<(srl (v16i8 (add v16i8:$vj, v16i8:$vk)), (v16i8 (vsplat_imm_eq_1))),
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(VAVG_BU v16i8:$vj, v16i8:$vk)>;
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def : Pat<(srl (v8i16 (add v8i16:$vj, v8i16:$vk)), (v8i16 (vsplat_imm_eq_1))),
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(VAVG_HU v8i16:$vj, v8i16:$vk)>;
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def : Pat<(srl (v4i32 (add v4i32:$vj, v4i32:$vk)), (v4i32 (vsplat_imm_eq_1))),
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(VAVG_WU v4i32:$vj, v4i32:$vk)>;
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def : Pat<(srl (v2i64 (add v2i64:$vj, v2i64:$vk)), (v2i64 (vsplat_imm_eq_1))),
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(VAVG_DU v2i64:$vj, v2i64:$vk)>;
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def : Pat<(sra (v16i8 (add (v16i8 (add v16i8:$vj, v16i8:$vk)),
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(v16i8 (vsplat_imm_eq_1)))),
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(v16i8 (vsplat_imm_eq_1))),
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(VAVGR_B v16i8:$vj, v16i8:$vk)>;
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def : Pat<(sra (v8i16 (add (v8i16 (add v8i16:$vj, v8i16:$vk)),
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(v8i16 (vsplat_imm_eq_1)))),
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(v8i16 (vsplat_imm_eq_1))),
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(VAVGR_H v8i16:$vj, v8i16:$vk)>;
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def : Pat<(sra (v4i32 (add (v4i32 (add v4i32:$vj, v4i32:$vk)),
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(v4i32 (vsplat_imm_eq_1)))),
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(v4i32 (vsplat_imm_eq_1))),
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(VAVGR_W v4i32:$vj, v4i32:$vk)>;
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def : Pat<(sra (v2i64 (add (v2i64 (add v2i64:$vj, v2i64:$vk)),
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(v2i64 (vsplat_imm_eq_1)))),
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(v2i64 (vsplat_imm_eq_1))),
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(VAVGR_D v2i64:$vj, v2i64:$vk)>;
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def : Pat<(srl (v16i8 (add (v16i8 (add v16i8:$vj, v16i8:$vk)),
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(v16i8 (vsplat_imm_eq_1)))),
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(v16i8 (vsplat_imm_eq_1))),
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(VAVGR_BU v16i8:$vj, v16i8:$vk)>;
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def : Pat<(srl (v8i16 (add (v8i16 (add v8i16:$vj, v8i16:$vk)),
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(v8i16 (vsplat_imm_eq_1)))),
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(v8i16 (vsplat_imm_eq_1))),
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(VAVGR_HU v8i16:$vj, v8i16:$vk)>;
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def : Pat<(srl (v4i32 (add (v4i32 (add v4i32:$vj, v4i32:$vk)),
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(v4i32 (vsplat_imm_eq_1)))),
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(v4i32 (vsplat_imm_eq_1))),
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(VAVGR_WU v4i32:$vj, v4i32:$vk)>;
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def : Pat<(srl (v2i64 (add (v2i64 (add v2i64:$vj, v2i64:$vk)),
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(v2i64 (vsplat_imm_eq_1)))),
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(v2i64 (vsplat_imm_eq_1))),
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(VAVGR_DU v2i64:$vj, v2i64:$vk)>;
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// abs
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def : Pat<(abs v16i8:$vj), (VSIGNCOV_B v16i8:$vj, v16i8:$vj)>;
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def : Pat<(abs v8i16:$vj), (VSIGNCOV_H v8i16:$vj, v8i16:$vj)>;

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