Skip to content

Commit 63194c2

Browse files
4vtomat4vtomat
committed
fixup! cleanup, typo, subtarget
1 parent bba3c88 commit 63194c2

File tree

10 files changed

+32
-31
lines changed

10 files changed

+32
-31
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -809,7 +809,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
809809

810810
bool isSImm5() const { return isSImm<5>(); }
811811
bool isSImm6() const { return isSImm<6>(); }
812-
bool isSImm8() const { return isSImm<8>(); }
813812
bool isSImm10() const { return isSImm<10>(); }
814813
bool isSImm11() const { return isSImm<11>(); }
815814
bool isSImm12() const { return isSImm<12>(); }

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1104,10 +1104,6 @@ def FeatureStdExtP
11041104
def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
11051105
AssemblerPredicate<(all_of FeatureStdExtP),
11061106
"'Base P' (Packed SIMD)">;
1107-
def FeatureEnablePExtCodeGen
1108-
: SubtargetFeature<"enable-p-ext-codegen", "EnablePExtCodeGen",
1109-
"true", "Turn on P Extension codegen(This is a temporary"
1110-
" switch where only partial codegen is currently supported)">;
11111107

11121108
def HasStdExtZbaOrP
11131109
: Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1047,10 +1047,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
10471047
Imm = SignExtend64<32>(Imm);
10481048

10491049
if (hasAllWUsers(Node) && isApplicableToPLI(Imm) &&
1050-
Subtarget->hasStdExtP() && Subtarget->enablePExtCodeGen()) {
1051-
// If its 4 packed 8 bit integer or 2 packed signed integer, we can simply
1052-
// copy lower 32 bits to higher 32 bits to make it able to rematerialize
1053-
// to PLI_B or PLI_H
1050+
Subtarget->enablePExtCodeGen()) {
1051+
// If its 4 packed 8-bit integers or 2 packed signed 16-bit integers, we
1052+
// can simply copy lower 32 bits to higher 32 bits to make it able to
1053+
// rematerialize to PLI_B or PLI_H
10541054
Imm = ((uint64_t)Imm << 32) | (Imm & 0xFFFFFFFF);
10551055
}
10561056

@@ -2674,7 +2674,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
26742674
CurDAG->RemoveDeadNode(Node);
26752675
return;
26762676
}
2677-
if (Subtarget->hasStdExtP() && Subtarget->enablePExtCodeGen()) {
2677+
if (Subtarget->enablePExtCodeGen()) {
26782678
if (((VT == MVT::v4i16 || VT == MVT::v8i8) && SrcVT == MVT::i64) ||
26792679
((SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) && VT == MVT::i64)) {
26802680
ReplaceUses(SDValue(Node, 0), Node->getOperand(0));

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
280280
}
281281

282282
// fixed vector is stored in GPRs for P extension packed operations
283-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen()) {
283+
if (Subtarget.enablePExtCodeGen()) {
284284
if (Subtarget.is64Bit()) {
285285
addRegisterClass(MVT::v2i32, &RISCV::GPRRegClass);
286286
addRegisterClass(MVT::v4i16, &RISCV::GPRRegClass);
@@ -499,7 +499,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
499499
ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
500500
ISD::FROUNDEVEN, ISD::FCANONICALIZE};
501501

502-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen()) {
502+
if (Subtarget.enablePExtCodeGen()) {
503503
setTargetDAGCombine(ISD::TRUNCATE);
504504
setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
505505
setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
@@ -1748,8 +1748,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
17481748

17491749
TargetLoweringBase::LegalizeTypeAction
17501750
RISCVTargetLowering::getPreferredVectorAction(MVT VT) const {
1751-
if (Subtarget.hasStdExtP() && Subtarget.is64Bit() &&
1752-
Subtarget.enablePExtCodeGen())
1751+
if (Subtarget.is64Bit() && Subtarget.enablePExtCodeGen())
17531752
if (VT == MVT::v2i16 || VT == MVT::v4i8)
17541753
return TypeWidenVector;
17551754

@@ -4372,7 +4371,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
43724371

43734372
SDLoc DL(Op);
43744373
// Handle P extension packed vector BUILD_VECTOR with PLI for splat constants
4375-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen()) {
4374+
if (Subtarget.enablePExtCodeGen()) {
43764375
bool IsPExtVector =
43774376
(VT == MVT::v2i16 || VT == MVT::v4i8) ||
43784377
(Subtarget.is64Bit() &&
@@ -7553,7 +7552,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
75537552
return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
75547553
}
75557554

7556-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen()) {
7555+
if (Subtarget.enablePExtCodeGen()) {
75577556
bool Is32BitCast =
75587557
(VT == MVT::i32 && (Op0VT == MVT::v4i8 || Op0VT == MVT::v2i16)) ||
75597558
(Op0VT == MVT::i32 && (VT == MVT::v4i8 || VT == MVT::v2i16));
@@ -8238,7 +8237,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
82388237
auto *Store = cast<StoreSDNode>(Op);
82398238
SDValue StoredVal = Store->getValue();
82408239
EVT VT = StoredVal.getValueType();
8241-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen()) {
8240+
if (Subtarget.enablePExtCodeGen()) {
82428241
if (VT == MVT::v2i16 || VT == MVT::v4i8) {
82438242
SDValue DL(Op);
82448243
SDValue Cast = DAG.getBitcast(MVT::i32, StoredVal);
@@ -10531,8 +10530,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
1053110530
return DAG.getNode(RISCVISD::FMV_H_X, DL, EltVT, IntExtract);
1053210531
}
1053310532

10534-
if (Subtarget.hasStdExtP() && Subtarget.enablePExtCodeGen() &&
10535-
VecVT.isFixedLengthVector()) {
10533+
if (Subtarget.enablePExtCodeGen() && VecVT.isFixedLengthVector()) {
1053610534
if (VecVT != MVT::v4i16 && VecVT != MVT::v2i16 && VecVT != MVT::v8i8 &&
1053710535
VecVT != MVT::v4i8 && VecVT != MVT::v2i32)
1053810536
return SDValue();
@@ -14694,8 +14692,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
1469414692
return;
1469514693
}
1469614694

14697-
if (Subtarget.hasStdExtP() && Subtarget.is64Bit() &&
14698-
Subtarget.enablePExtCodeGen()) {
14695+
if (Subtarget.is64Bit() && Subtarget.enablePExtCodeGen()) {
1469914696
SDLoc DL(N);
1470014697
SDValue ExtLoad =
1470114698
DAG.getExtLoad(ISD::SEXTLOAD, DL, MVT::i64, Ld->getChain(),
@@ -16262,8 +16259,7 @@ static SDValue performTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
1626216259
SDValue N0 = N->getOperand(0);
1626316260
EVT VT = N->getValueType(0);
1626416261

16265-
if (Subtarget.hasStdExtP() && VT.isFixedLengthVector() &&
16266-
Subtarget.enablePExtCodeGen())
16262+
if (VT.isFixedLengthVector() && Subtarget.enablePExtCodeGen())
1626716263
return combinePExtTruncate(N, DAG, Subtarget);
1626816264

1626916265
// Pre-promote (i1 (truncate (srl X, Y))) on RV64 with Zbs without zero

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,12 @@ static cl::opt<bool> UseMIPSCCMovInsn("use-riscv-mips-ccmov",
6969
cl::desc("Use 'mips.ccmov' instruction"),
7070
cl::init(true), cl::Hidden);
7171

72+
static cl::opt<bool> EnablePExtCodeGen(
73+
"enable-p-ext-codegen",
74+
cl::desc("Turn on P Extension codegen(This is a temporary switch where "
75+
"only partial codegen is currently supported)"),
76+
cl::init(false), cl::Hidden);
77+
7278
void RISCVSubtarget::anchor() {}
7379

7480
RISCVSubtarget &
@@ -145,6 +151,10 @@ bool RISCVSubtarget::useConstantPoolForLargeInts() const {
145151
return !RISCVDisableUsingConstantPoolForLargeInts;
146152
}
147153

154+
bool RISCVSubtarget::enablePExtCodeGen() const {
155+
return HasStdExtP && EnablePExtCodeGen;
156+
}
157+
148158
unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
149159
// Loading integer from constant pool needs two instructions (the reason why
150160
// the minimum cost is 2): an address calculation instruction and a load

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -322,6 +322,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
322322
}
323323
}
324324

325+
bool enablePExtCodeGen() const;
326+
325327
// Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
326328
// vector hardware implementation which may be less than VLEN.
327329
unsigned getDLenFactor() const {

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -972,7 +972,7 @@ InstructionCost RISCVTTIImpl::getScalarizationOverhead(
972972
// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
973973
// For now, skip all fixed vector cost analysis when P extension is available
974974
// to avoid crashes in getMinRVVVectorSizeInBits()
975-
if (ST->hasStdExtP() && ST->enablePExtCodeGen() && isa<FixedVectorType>(Ty)) {
975+
if (ST->enablePExtCodeGen() && isa<FixedVectorType>(Ty)) {
976976
return 1; // Treat as single instruction cost for now
977977
}
978978

@@ -1635,7 +1635,7 @@ InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
16351635
// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
16361636
// For now, skip all fixed vector cost analysis when P extension is available
16371637
// to avoid crashes in getMinRVVVectorSizeInBits()
1638-
if (ST->hasStdExtP() && ST->enablePExtCodeGen() &&
1638+
if (ST->enablePExtCodeGen() &&
16391639
(isa<FixedVectorType>(Dst) || isa<FixedVectorType>(Src))) {
16401640
return 1; // Treat as single instruction cost for now
16411641
}
@@ -2339,8 +2339,7 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
23392339
// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
23402340
// For now, skip all fixed vector cost analysis when P extension is available
23412341
// to avoid crashes in getMinRVVVectorSizeInBits()
2342-
if (ST->hasStdExtP() && ST->enablePExtCodeGen() &&
2343-
isa<FixedVectorType>(Val)) {
2342+
if (ST->enablePExtCodeGen() && isa<FixedVectorType>(Val)) {
23442343
return 1; // Treat as single instruction cost for now
23452344
}
23462345

‎llvm/test/CodeGen/RISCV/features-info.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@
2323
; CHECK-NEXT: disable-postmisched-store-clustering - Disable PostRA store clustering in the machine scheduler.
2424
; CHECK-NEXT: dlen-factor-2 - Vector unit DLEN(data path width) is half of VLEN.
2525
; CHECK-NEXT: e - 'E' (Embedded Instruction Set with 16 GPRs).
26-
; CHECK-NEXT: enable-p-ext-codegen - Turn on P Extension codegen(This is a temporary switch where only partial codegen is currently supported).
2726
; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation).
2827
; CHECK-NEXT: experimental - Experimental intrinsics.
2928
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).

‎llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV32 %s
3-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
2+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV32 %s
3+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
44

55
; Test basic add/sub operations for v2i16
66
define void @test_padd_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {

‎llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -enable-p-ext-codegen -verify-machineinstrs < %s | FileCheck %s
33

44
; Test basic add/sub operations for v4i16
55
define void @test_padd_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {

0 commit comments

Comments
 (0)