[AArch64] Run CSE one last time

AZero13 · AZero13 · commit 63225d01f992 · 2025-08-12T21:08:31.000-04:00
During comparison optimization, many subs become sub, which is good. However, this means that now there are new cse opportunities that can be exploited because now, NZCV is no longer a use in those instructions.

This will come into play more as I set ADDS to be the default rather than add for CSE purposes.
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -788,8 +788,21 @@ void AArch64PassConfig::addMachineSSAOptimization() {
   // Run default MachineSSAOptimization first.
   TargetPassConfig::addMachineSSAOptimization();
 
+  // With optimization, dead code should already be eliminated. However
+  // there is one known exception: peephole optimizations may open more
+  // opportunities for dead code. This is especially true for targets whose
+  // peephole optimizations like ARM and AArch64 where dead defs to the flag
+  // register are removed, which previously prevented CSE.
+  addPass(&MachineCSELegacyID);
+  addPass(&MachineSinkingLegacyID);
+
   if (TM->getOptLevel() != CodeGenOptLevel::None)
     addPass(createAArch64MIPeepholeOptPass());
+
+  // Clean-up any last code that can be eliminated
+  // Due to the fact that the demotion of some instructions
+  // can result in the removal of instructions previously unable to be removed
+  addPass(&DeadMachineInstructionElimID);
 }
 
 bool AArch64PassConfig::addILPOpts() {
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -162,6 +162,8 @@
 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       AArch64 MI Peephole Optimization pass
 ; CHECK-NEXT:       AArch64 Dead register definitions
+; CHECK-NEXT:       Machine Common Subexpression Elimination
+; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       Detect Dead Lanes
 ; CHECK-NEXT:       Init Undef Pass
 ; CHECK-NEXT:       Process Implicit Definitions
diff --git a/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll b/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
@@ -206,13 +206,12 @@ define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) {
 ; CHECK-LABEL: insert_vec_v8i16_uaddlv_from_v8i16:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    stp xzr, xzr, [x0, #16]
-; CHECK-NEXT:    uaddlv.8h s0, v0
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    ushll.4s v1, v1, #0
-; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    str q1, [x0]
+; CHECK-NEXT:    uaddlv.8h s1, v0
+; CHECK-NEXT:    mov.h v0[0], v1[0]
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ucvtf.4s v0, v0
+; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -228,14 +227,13 @@ define void @insert_vec_v3i16_uaddlv_from_v8i16(ptr %0) {
 ; CHECK-LABEL: insert_vec_v3i16_uaddlv_from_v8i16:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    add x8, x0, #8
-; CHECK-NEXT:    uaddlv.8h s0, v0
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    ushll.4s v1, v1, #0
-; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    st1.s { v1 }[2], [x8]
-; CHECK-NEXT:    str d1, [x0]
+; CHECK-NEXT:    uaddlv.8h s1, v0
+; CHECK-NEXT:    mov.h v0[0], v1[0]
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ucvtf.4s v0, v0
+; CHECK-NEXT:    st1.s { v0 }[2], [x8]
+; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -283,9 +281,9 @@ define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) {
 ; CHECK-NEXT:    stp q0, q0, [x0, #32]
 ; CHECK-NEXT:    mov.h v2[0], v1[0]
 ; CHECK-NEXT:    bic.4h v2, #255, lsl #8
-; CHECK-NEXT:    ushll.4s v2, v2, #0
-; CHECK-NEXT:    ucvtf.4s v2, v2
-; CHECK-NEXT:    stp q2, q0, [x0]
+; CHECK-NEXT:    ushll.4s v1, v2, #0
+; CHECK-NEXT:    ucvtf.4s v1, v1
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -386,12 +384,11 @@ define void @insert_vec_v4i16_uaddlv_from_v4i32(ptr %0) {
 ; CHECK-LABEL: insert_vec_v4i16_uaddlv_from_v4i32:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
-; CHECK-NEXT:    uaddlv.4s d0, v0
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    ushll.4s v1, v1, #0
-; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    str q1, [x0]
+; CHECK-NEXT:    uaddlv.4s d1, v0
+; CHECK-NEXT:    mov.h v0[0], v1[0]
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ucvtf.4s v0, v0
+; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -407,14 +404,13 @@ define void @insert_vec_v16i16_uaddlv_from_v4i32(ptr %0) {
 ; CHECK-LABEL: insert_vec_v16i16_uaddlv_from_v4i32:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    movi.2d v2, #0000000000000000
-; CHECK-NEXT:    uaddlv.4s d0, v0
-; CHECK-NEXT:    stp q2, q2, [x0, #32]
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    ushll.4s v1, v1, #0
+; CHECK-NEXT:    uaddlv.4s d1, v0
+; CHECK-NEXT:    stp q0, q0, [x0, #32]
+; CHECK-NEXT:    mov.h v2[0], v1[0]
+; CHECK-NEXT:    ushll.4s v1, v2, #0
 ; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    stp q1, q2, [x0]
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -430,14 +426,13 @@ define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) {
 ; CHECK-LABEL: insert_vec_v8i8_uaddlv_from_v4i32:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    stp xzr, xzr, [x0, #16]
-; CHECK-NEXT:    uaddlv.4s d0, v0
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    bic.4h v1, #255, lsl #8
-; CHECK-NEXT:    ushll.4s v1, v1, #0
-; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    str q1, [x0]
+; CHECK-NEXT:    uaddlv.4s d1, v0
+; CHECK-NEXT:    mov.h v0[0], v1[0]
+; CHECK-NEXT:    bic.4h v0, #255, lsl #8
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ucvtf.4s v0, v0
+; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
@@ -453,15 +448,14 @@ define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {
 ; CHECK-LABEL: insert_vec_v16i8_uaddlv_from_v4i32:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    movi.2d v2, #0000000000000000
-; CHECK-NEXT:    uaddlv.4s d0, v0
-; CHECK-NEXT:    stp q2, q2, [x0, #32]
-; CHECK-NEXT:    mov.h v1[0], v0[0]
-; CHECK-NEXT:    bic.4h v1, #255, lsl #8
-; CHECK-NEXT:    ushll.4s v1, v1, #0
+; CHECK-NEXT:    uaddlv.4s d1, v0
+; CHECK-NEXT:    stp q0, q0, [x0, #32]
+; CHECK-NEXT:    mov.h v2[0], v1[0]
+; CHECK-NEXT:    bic.4h v2, #255, lsl #8
+; CHECK-NEXT:    ushll.4s v1, v2, #0
 ; CHECK-NEXT:    ucvtf.4s v1, v1
-; CHECK-NEXT:    stp q1, q2, [x0]
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
 
 entry:
diff --git a/llvm/test/CodeGen/AArch64/addsub-shifted-reg-cheap-as-move.ll b/llvm/test/CodeGen/AArch64/addsub-shifted-reg-cheap-as-move.ll
@@ -97,15 +97,13 @@ define void @f1(i1 %c0, i1 %c1, ptr %a, i64 %i) {
 ; LSLFAST-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
 ; LSLFAST-NEXT:    .cfi_def_cfa_offset 16
 ; LSLFAST-NEXT:    .cfi_offset w30, -16
-; LSLFAST-NEXT:    add x8, x2, x3, lsl #4
+; LSLFAST-NEXT:    add x0, x2, x3, lsl #4
 ; LSLFAST-NEXT:    tbz w1, #0, .LBB1_3
 ; LSLFAST-NEXT:  // %bb.2: // %B
-; LSLFAST-NEXT:    mov x0, x8
 ; LSLFAST-NEXT:    bl g
 ; LSLFAST-NEXT:    b .LBB1_4
 ; LSLFAST-NEXT:  .LBB1_3: // %C
-; LSLFAST-NEXT:    add x0, x2, x3, lsl #4
-; LSLFAST-NEXT:    mov x1, x8
+; LSLFAST-NEXT:    mov x1, x0
 ; LSLFAST-NEXT:    bl g
 ; LSLFAST-NEXT:  .LBB1_4:
 ; LSLFAST-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops.ll b/llvm/test/CodeGen/AArch64/atomic-ops.ll
@@ -133,9 +133,9 @@ define dso_local i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
 ; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i8:
 ; OUTLINE_ATOMICS:       // %bb.0:
 ; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd1_relax
 ; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; OUTLINE_ATOMICS-NEXT:    ret
@@ -161,9 +161,9 @@ define dso_local i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
 ; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i16:
 ; OUTLINE_ATOMICS:       // %bb.0:
 ; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd2_rel
 ; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; OUTLINE_ATOMICS-NEXT:    ret
@@ -189,9 +189,9 @@ define dso_local i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
 ; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i32:
 ; OUTLINE_ATOMICS:       // %bb.0:
 ; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
 ; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
 ; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; OUTLINE_ATOMICS-NEXT:    ret
@@ -217,9 +217,9 @@ define dso_local i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
 ; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i64:
 ; OUTLINE_ATOMICS:       // %bb.0:
 ; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
-; OUTLINE_ATOMICS-NEXT:    neg x0, x0
 ; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
 ; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    neg x0, x0
 ; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
 ; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; OUTLINE_ATOMICS-NEXT:    ret
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -749,41 +749,38 @@ define <8 x i64> @combine_vec_sdiv_by_pow2b_v8i64(<8 x i64> %x) {
 ; CHECK-GI-NEXT:    mov v4.h[1], w9
 ; CHECK-GI-NEXT:    neg v5.2d, v5.2d
 ; CHECK-GI-NEXT:    ldr q19, [x8, :lo12:.LCPI23_3]
-; CHECK-GI-NEXT:    neg v19.2d, v19.2d
 ; CHECK-GI-NEXT:    ushl v7.2d, v7.2d, v5.2d
 ; CHECK-GI-NEXT:    ushl v5.2d, v17.2d, v5.2d
+; CHECK-GI-NEXT:    neg v17.2d, v19.2d
 ; CHECK-GI-NEXT:    mov v4.h[2], w9
 ; CHECK-GI-NEXT:    add v7.2d, v0.2d, v7.2d
 ; CHECK-GI-NEXT:    add v5.2d, v2.2d, v5.2d
 ; CHECK-GI-NEXT:    mov v4.h[3], w9
 ; CHECK-GI-NEXT:    adrp x9, .LCPI23_0
 ; CHECK-GI-NEXT:    ldr q6, [x9, :lo12:.LCPI23_0]
 ; CHECK-GI-NEXT:    adrp x9, .LCPI23_2
-; CHECK-GI-NEXT:    sshl v7.2d, v7.2d, v19.2d
+; CHECK-GI-NEXT:    sshl v7.2d, v7.2d, v17.2d
 ; CHECK-GI-NEXT:    ldr q20, [x9, :lo12:.LCPI23_2]
-; CHECK-GI-NEXT:    sshl v5.2d, v5.2d, v19.2d
+; CHECK-GI-NEXT:    sshl v5.2d, v5.2d, v17.2d
 ; CHECK-GI-NEXT:    neg v6.2d, v6.2d
 ; CHECK-GI-NEXT:    ushll v4.4s, v4.4h, #0
-; CHECK-GI-NEXT:    neg v20.2d, v20.2d
 ; CHECK-GI-NEXT:    ushl v16.2d, v16.2d, v6.2d
 ; CHECK-GI-NEXT:    ushl v6.2d, v18.2d, v6.2d
-; CHECK-GI-NEXT:    ushll v17.2d, v4.2s, #0
-; CHECK-GI-NEXT:    ushll2 v18.2d, v4.4s, #0
-; CHECK-GI-NEXT:    ushll v4.2d, v4.2s, #0
+; CHECK-GI-NEXT:    neg v18.2d, v20.2d
+; CHECK-GI-NEXT:    ushll v21.2d, v4.2s, #0
+; CHECK-GI-NEXT:    ushll2 v4.2d, v4.4s, #0
 ; CHECK-GI-NEXT:    add v16.2d, v1.2d, v16.2d
 ; CHECK-GI-NEXT:    add v6.2d, v3.2d, v6.2d
-; CHECK-GI-NEXT:    shl v17.2d, v17.2d, #63
-; CHECK-GI-NEXT:    shl v18.2d, v18.2d, #63
+; CHECK-GI-NEXT:    shl v19.2d, v21.2d, #63
 ; CHECK-GI-NEXT:    shl v4.2d, v4.2d, #63
-; CHECK-GI-NEXT:    sshl v16.2d, v16.2d, v20.2d
-; CHECK-GI-NEXT:    sshl v6.2d, v6.2d, v20.2d
-; CHECK-GI-NEXT:    sshr v17.2d, v17.2d, #63
-; CHECK-GI-NEXT:    sshr v18.2d, v18.2d, #63
+; CHECK-GI-NEXT:    sshl v16.2d, v16.2d, v18.2d
+; CHECK-GI-NEXT:    sshl v6.2d, v6.2d, v18.2d
+; CHECK-GI-NEXT:    sshr v19.2d, v19.2d, #63
 ; CHECK-GI-NEXT:    sshr v4.2d, v4.2d, #63
-; CHECK-GI-NEXT:    bif v0.16b, v7.16b, v17.16b
-; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v18.16b
-; CHECK-GI-NEXT:    bif v2.16b, v5.16b, v4.16b
-; CHECK-GI-NEXT:    bif v3.16b, v6.16b, v18.16b
+; CHECK-GI-NEXT:    bif v0.16b, v7.16b, v19.16b
+; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v4.16b
+; CHECK-GI-NEXT:    bif v2.16b, v5.16b, v19.16b
+; CHECK-GI-NEXT:    bif v3.16b, v6.16b, v4.16b
 ; CHECK-GI-NEXT:    ret
   %1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16>
   ret <8 x i64> %1
diff --git a/llvm/test/CodeGen/AArch64/concat-vector.ll b/llvm/test/CodeGen/AArch64/concat-vector.ll
@@ -272,9 +272,9 @@ define <4 x i16> @concat_undef_first_use_first(ptr %p1, ptr %p2) {
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    ldrh w8, [x0]
 ; CHECK-GI-NEXT:    ldrh w9, [x0, #2]
-; CHECK-GI-NEXT:    fmov s1, w8
-; CHECK-GI-NEXT:    mov v1.h[1], w9
-; CHECK-GI-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT:    fmov s0, w8
+; CHECK-GI-NEXT:    mov v0.h[1], w9
+; CHECK-GI-NEXT:    mov v0.s[1], v0.s[0]
 ; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-GI-NEXT:    ret
   %l1 = load <2 x i16>, ptr %p1
@@ -295,9 +295,9 @@ define <4 x i16> @concat_undef_first_use_second(ptr %p1, ptr %p2) {
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    ldrh w8, [x0]
 ; CHECK-GI-NEXT:    ldrh w9, [x0, #2]
-; CHECK-GI-NEXT:    fmov s1, w8
-; CHECK-GI-NEXT:    mov v1.h[1], w9
-; CHECK-GI-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT:    fmov s0, w8
+; CHECK-GI-NEXT:    mov v0.h[1], w9
+; CHECK-GI-NEXT:    mov v0.s[1], v0.s[0]
 ; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-GI-NEXT:    ret
   %l1 = load <2 x i16>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/fabs-fp128.ll b/llvm/test/CodeGen/AArch64/fabs-fp128.ll
@@ -144,22 +144,21 @@ define <4 x fp128> @fabs_v4f128(<4 x fp128> %a) {
 ; CHECK-GI-LABEL: fabs_v4f128:
 ; CHECK-GI:       // %bb.0: // %entry
 ; CHECK-GI-NEXT:    mov x8, v0.d[1]
-; CHECK-GI-NEXT:    mov v7.d[0], v0.d[0]
+; CHECK-GI-NEXT:    mov v0.d[0], v0.d[0]
 ; CHECK-GI-NEXT:    mov x9, v1.d[1]
 ; CHECK-GI-NEXT:    mov x10, v2.d[1]
 ; CHECK-GI-NEXT:    mov x11, v3.d[1]
 ; CHECK-GI-NEXT:    mov v1.d[0], v1.d[0]
 ; CHECK-GI-NEXT:    mov v2.d[0], v2.d[0]
 ; CHECK-GI-NEXT:    mov v3.d[0], v3.d[0]
 ; CHECK-GI-NEXT:    and x8, x8, #0x7fffffffffffffff
-; CHECK-GI-NEXT:    mov v7.d[1], x8
+; CHECK-GI-NEXT:    mov v0.d[1], x8
 ; CHECK-GI-NEXT:    and x8, x9, #0x7fffffffffffffff
 ; CHECK-GI-NEXT:    and x9, x10, #0x7fffffffffffffff
 ; CHECK-GI-NEXT:    and x10, x11, #0x7fffffffffffffff
 ; CHECK-GI-NEXT:    mov v1.d[1], x8
 ; CHECK-GI-NEXT:    mov v2.d[1], x9
 ; CHECK-GI-NEXT:    mov v3.d[1], x10
-; CHECK-GI-NEXT:    mov v0.16b, v7.16b
 ; CHECK-GI-NEXT:    ret
 entry:
   %c = call <4 x fp128> @llvm.fabs.v4f128(<4 x fp128> %a)
diff --git a/llvm/test/CodeGen/AArch64/rem.ll b/llvm/test/CodeGen/AArch64/rem.ll
