Skip to content

Commit 6362388

Browse files
committed
Recode with array indexing
Signed-off-by: John Lu <[email protected]>
1 parent 7b967f1 commit 6362388

File tree

1 file changed

+8
-6
lines changed

1 file changed

+8
-6
lines changed

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4096,8 +4096,8 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
40964096

40974097
EVT ElementType = VT.getScalarType();
40984098
EVT TargetScalarType = ElementType.getHalfSizedIntegerVT(*DAG.getContext());
4099-
EVT TargetType = (VT.isVector() ? VT.changeVectorElementType(TargetScalarType)
4100-
: TargetScalarType);
4099+
EVT TargetType = VT.isVector() ? VT.changeVectorElementType(TargetScalarType)
4100+
: TargetScalarType;
41014101

41024102
if (Known.getMinValue().getZExtValue() < TargetScalarType.getSizeInBits())
41034103
return SDValue();
@@ -4125,11 +4125,13 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
41254125
if (VT.isVector()) {
41264126
EVT ConcatType = TargetType.getDoubleNumVectorElementsVT(*DAG.getContext());
41274127
unsigned NElts = TargetType.getVectorNumElements();
4128-
SmallVector<SDValue, 8> Ops;
4129-
DAG.ExtractVectorElements(NewShift, Ops, 0, NElts);
4128+
SmallVector<SDValue, 8> HiOps;
4129+
SmallVector<SDValue, 16> HiAndLoOps(NElts * 2, Zero);
4130+
4131+
DAG.ExtractVectorElements(NewShift, HiOps, 0, NElts);
41304132
for (unsigned I = 0; I != NElts; ++I)
4131-
Ops.insert(Ops.begin() + 2 * I, Zero);
4132-
Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, ConcatType, Ops);
4133+
HiAndLoOps[2 * I + 1] = HiOps[I];
4134+
Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, ConcatType, HiAndLoOps);
41334135
} else {
41344136
EVT ConcatType = EVT::getVectorVT(*DAG.getContext(), TargetType, 2);
41354137
Vec = DAG.getBuildVector(ConcatType, SL, {Zero, NewShift});

0 commit comments

Comments
 (0)