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AMDGPU: Remove override of TargetInstrInfo::getRegClass
This should not be overridable and the special case hacks have been replaced with RegClassByHwMode
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-17
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2 files changed

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-17
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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -5954,19 +5954,6 @@ SIInstrInfo::getWholeWaveFunctionSetup(MachineFunction &MF) const {
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llvm_unreachable("Couldn't find SI_SETUP_WHOLE_WAVE_FUNC instruction");
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}
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5957-
// FIXME: This should not be an overridable function. All subtarget dependent
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// operand modifications should go through isLookupRegClassByHwMode in the
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// generic handling.
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const TargetRegisterClass *
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SIInstrInfo::getRegClass(const MCInstrDesc &TID, unsigned OpNum,
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const TargetRegisterInfo *TRI) const {
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if (OpNum >= TID.getNumOperands())
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return nullptr;
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const MCOperandInfo &OpInfo = TID.operands()[OpNum];
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int16_t RegClass = getOpRegClassID(OpInfo);
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return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
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}
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const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const {
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const MCInstrDesc &Desc = get(MI.getOpcode());

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1539,10 +1539,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
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/// Return true if this opcode should not be used by codegen.
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bool isAsmOnlyOpcode(int MCOp) const;
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1542-
const TargetRegisterClass *
1543-
getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1544-
const TargetRegisterInfo *TRI) const override;
1545-
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void fixImplicitOperands(MachineInstr &MI) const;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,

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