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[NFC][MC][Sparc] Minor code cleanup in Sparc disassembler (#154823)
- use llvm::endian::read<> to read bit/little endian. - Range check against size of the lookup tables instead of hardcoded numbers. - Make lookup tables constexpr. - Drop {} for single-statement if-else.
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llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

Lines changed: 33 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "llvm/MC/MCInst.h"
2121
#include "llvm/MC/TargetRegistry.h"
2222
#include "llvm/Support/Compiler.h"
23+
#include "llvm/Support/Endian.h"
2324

2425
using namespace llvm;
2526
using namespace llvm::MCD;
@@ -60,7 +61,8 @@ LLVMInitializeSparcDisassembler() {
6061
createSparcDisassembler);
6162
}
6263

63-
static const unsigned IntRegDecoderTable[] = {
64+
// clang-format off
65+
static constexpr unsigned IntRegDecoderTable[] = {
6466
SP::G0, SP::G1, SP::G2, SP::G3,
6567
SP::G4, SP::G5, SP::G6, SP::G7,
6668
SP::O0, SP::O1, SP::O2, SP::O3,
@@ -70,7 +72,7 @@ static const unsigned IntRegDecoderTable[] = {
7072
SP::I0, SP::I1, SP::I2, SP::I3,
7173
SP::I4, SP::I5, SP::I6, SP::I7 };
7274

73-
static const unsigned FPRegDecoderTable[] = {
75+
static constexpr unsigned FPRegDecoderTable[] = {
7476
SP::F0, SP::F1, SP::F2, SP::F3,
7577
SP::F4, SP::F5, SP::F6, SP::F7,
7678
SP::F8, SP::F9, SP::F10, SP::F11,
@@ -80,7 +82,7 @@ static const unsigned FPRegDecoderTable[] = {
8082
SP::F24, SP::F25, SP::F26, SP::F27,
8183
SP::F28, SP::F29, SP::F30, SP::F31 };
8284

83-
static const unsigned DFPRegDecoderTable[] = {
85+
static constexpr unsigned DFPRegDecoderTable[] = {
8486
SP::D0, SP::D16, SP::D1, SP::D17,
8587
SP::D2, SP::D18, SP::D3, SP::D19,
8688
SP::D4, SP::D20, SP::D5, SP::D21,
@@ -90,7 +92,7 @@ static const unsigned DFPRegDecoderTable[] = {
9092
SP::D12, SP::D28, SP::D13, SP::D29,
9193
SP::D14, SP::D30, SP::D15, SP::D31 };
9294

93-
static const unsigned QFPRegDecoderTable[] = {
95+
static constexpr unsigned QFPRegDecoderTable[] = {
9496
SP::Q0, SP::Q8, ~0U, ~0U,
9597
SP::Q1, SP::Q9, ~0U, ~0U,
9698
SP::Q2, SP::Q10, ~0U, ~0U,
@@ -100,29 +102,29 @@ static const unsigned QFPRegDecoderTable[] = {
100102
SP::Q6, SP::Q14, ~0U, ~0U,
101103
SP::Q7, SP::Q15, ~0U, ~0U } ;
102104

103-
static const unsigned FCCRegDecoderTable[] = {
105+
static constexpr unsigned FCCRegDecoderTable[] = {
104106
SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
105107

106-
static const unsigned ASRRegDecoderTable[] = {
108+
static constexpr unsigned ASRRegDecoderTable[] = {
107109
SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6,
108110
SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,
109111
SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,
110112
SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
111113
SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
112114

113-
static const unsigned PRRegDecoderTable[] = {
115+
static constexpr unsigned PRRegDecoderTable[] = {
114116
SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK,
115117
SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP,
116118
SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE};
117119

118-
static const uint16_t IntPairDecoderTable[] = {
120+
static constexpr uint16_t IntPairDecoderTable[] = {
119121
SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
120122
SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
121123
SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
122124
SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
123125
};
124126

125-
static const unsigned CPRegDecoderTable[] = {
127+
static constexpr unsigned CPRegDecoderTable[] = {
126128
SP::C0, SP::C1, SP::C2, SP::C3,
127129
SP::C4, SP::C5, SP::C6, SP::C7,
128130
SP::C8, SP::C9, SP::C10, SP::C11,
@@ -133,18 +135,18 @@ static const unsigned CPRegDecoderTable[] = {
133135
SP::C28, SP::C29, SP::C30, SP::C31
134136
};
135137

136-
137-
static const uint16_t CPPairDecoderTable[] = {
138+
static constexpr uint16_t CPPairDecoderTable[] = {
138139
SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
139140
SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
140141
SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
141142
SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
142143
};
144+
// clang-format on
143145

144146
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
145147
uint64_t Address,
146148
const MCDisassembler *Decoder) {
147-
if (RegNo > 31)
149+
if (RegNo >= std::size(IntRegDecoderTable))
148150
return MCDisassembler::Fail;
149151
unsigned Reg = IntRegDecoderTable[RegNo];
150152
Inst.addOperand(MCOperand::createReg(Reg));
@@ -168,7 +170,7 @@ static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
168170
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
169171
uint64_t Address,
170172
const MCDisassembler *Decoder) {
171-
if (RegNo > 31)
173+
if (RegNo >= std::size(FPRegDecoderTable))
172174
return MCDisassembler::Fail;
173175
unsigned Reg = FPRegDecoderTable[RegNo];
174176
Inst.addOperand(MCOperand::createReg(Reg));
@@ -178,7 +180,7 @@ static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
178180
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
179181
uint64_t Address,
180182
const MCDisassembler *Decoder) {
181-
if (RegNo > 31)
183+
if (RegNo >= std::size(DFPRegDecoderTable))
182184
return MCDisassembler::Fail;
183185
unsigned Reg = DFPRegDecoderTable[RegNo];
184186
Inst.addOperand(MCOperand::createReg(Reg));
@@ -188,7 +190,7 @@ static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
188190
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
189191
uint64_t Address,
190192
const MCDisassembler *Decoder) {
191-
if (RegNo > 31)
193+
if (RegNo >= std::size(QFPRegDecoderTable))
192194
return MCDisassembler::Fail;
193195

194196
unsigned Reg = QFPRegDecoderTable[RegNo];
@@ -201,7 +203,7 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
201203
static DecodeStatus
202204
DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
203205
const MCDisassembler *Decoder) {
204-
if (RegNo > 31)
206+
if (RegNo >= std::size(CPRegDecoderTable))
205207
return MCDisassembler::Fail;
206208
unsigned Reg = CPRegDecoderTable[RegNo];
207209
Inst.addOperand(MCOperand::createReg(Reg));
@@ -211,7 +213,7 @@ DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
211213
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
212214
uint64_t Address,
213215
const MCDisassembler *Decoder) {
214-
if (RegNo > 3)
216+
if (RegNo >= std::size(FCCRegDecoderTable))
215217
return MCDisassembler::Fail;
216218
Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
217219
return MCDisassembler::Success;
@@ -220,7 +222,7 @@ static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
220222
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
221223
uint64_t Address,
222224
const MCDisassembler *Decoder) {
223-
if (RegNo > 31)
225+
if (RegNo >= std::size(ASRRegDecoderTable))
224226
return MCDisassembler::Fail;
225227
Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
226228
return MCDisassembler::Success;
@@ -240,24 +242,26 @@ static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
240242
const MCDisassembler *Decoder) {
241243
DecodeStatus S = MCDisassembler::Success;
242244

243-
if (RegNo > 31)
244-
return MCDisassembler::Fail;
245-
246245
if ((RegNo & 1))
247246
S = MCDisassembler::SoftFail;
248247

249-
unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
248+
RegNo = RegNo / 2;
249+
if (RegNo >= std::size(IntPairDecoderTable))
250+
return MCDisassembler::Fail;
251+
252+
unsigned RegisterPair = IntPairDecoderTable[RegNo];
250253
Inst.addOperand(MCOperand::createReg(RegisterPair));
251254
return S;
252255
}
253256

254257
static DecodeStatus
255258
DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
256259
const MCDisassembler *Decoder) {
257-
if (RegNo > 31)
260+
RegNo = RegNo / 2;
261+
if (RegNo >= std::size(CPPairDecoderTable))
258262
return MCDisassembler::Fail;
259263

260-
unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
264+
unsigned RegisterPair = CPPairDecoderTable[RegNo];
261265
Inst.addOperand(MCOperand::createReg(RegisterPair));
262266
return MCDisassembler::Success;
263267
}
@@ -285,12 +289,8 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
285289
}
286290

287291
Size = 4;
288-
Insn = IsLittleEndian
289-
? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
290-
(Bytes[3] << 24)
291-
: (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
292-
(Bytes[0] << 24);
293-
292+
Insn = support::endian::read<uint32_t>(
293+
Bytes.data(), IsLittleEndian ? endianness::little : endianness::big);
294294
return MCDisassembler::Success;
295295
}
296296

@@ -308,13 +308,11 @@ DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
308308
// Calling the auto-generated decoder function.
309309

310310
if (STI.hasFeature(Sparc::FeatureV9))
311-
{
312-
Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
313-
}
311+
Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address,
312+
this, STI);
314313
else
315-
{
316314
Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
317-
}
315+
318316
if (Result != MCDisassembler::Fail)
319317
return Result;
320318

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