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[AMDGPU][MC] Do not inline lit()/lit64() operands.
For now treat the modifiers synonymous to each other. The disassembler side is to be addressed separately.
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5 files changed

+417
-78
lines changed

5 files changed

+417
-78
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 34 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -2105,6 +2105,10 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
21052105
// Only plain immediates are inlinable (e.g. "clamp" attribute is not)
21062106
return false;
21072107
}
2108+
2109+
if (getModifiers().Lit != LitModifier::None)
2110+
return false;
2111+
21082112
// TODO: We should avoid using host float here. It would be better to
21092113
// check the float bit values which is what a few other places do.
21102114
// We've had bot failures before due to weird NaN support on mips hosts.
@@ -2349,7 +2353,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23492353
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
23502354
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
23512355
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2352-
if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
2356+
if (Lit == LitModifier::None &&
2357+
AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
23532358
AsmParser->hasInv2PiInlineImm())) {
23542359
Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
23552360
return;
@@ -2386,14 +2391,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23862391
Val = Hi_32(Val);
23872392
}
23882393
}
2389-
2390-
if (Lit != LitModifier::None) {
2391-
Inst.addOperand(
2392-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2393-
} else {
2394-
Inst.addOperand(MCOperand::createImm(Val));
2395-
}
2396-
return;
2394+
break;
23972395
}
23982396

23992397
// We don't allow fp literals in 64-bit integer instructions. It is
@@ -2405,20 +2403,14 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24052403
if (CanUse64BitLiterals && Lit == LitModifier::None &&
24062404
(isInt<32>(Val) || isUInt<32>(Val)))
24072405
Lit = LitModifier::Lit64;
2408-
2409-
if (Lit != LitModifier::None) {
2410-
Inst.addOperand(
2411-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2412-
} else {
2413-
Inst.addOperand(MCOperand::createImm(Val));
2414-
}
2415-
return;
2406+
break;
24162407

24172408
case AMDGPU::OPERAND_REG_IMM_BF16:
24182409
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
24192410
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
24202411
case AMDGPU::OPERAND_REG_IMM_V2BF16:
2421-
if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) {
2412+
if (Lit == LitModifier::None && AsmParser->hasInv2PiInlineImm() &&
2413+
Literal == 0x3fc45f306725feed) {
24222414
// This is the 1/(2*pi) which is going to be truncated to bf16 with the
24232415
// loss of precision. The constant represents ideomatic fp32 value of
24242416
// 1/(2*pi) = 0.15915494 since bf16 is in fact fp32 with cleared low 16
@@ -2456,14 +2448,19 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24562448
// We allow precision lost but not overflow or underflow. This should be
24572449
// checked earlier in isLiteralImm()
24582450

2459-
uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
2460-
Inst.addOperand(MCOperand::createImm(ImmVal));
2461-
return;
2451+
Val = FPLiteral.bitcastToAPInt().getZExtValue();
2452+
break;
24622453
}
24632454
default:
24642455
llvm_unreachable("invalid operand size");
24652456
}
24662457

2458+
if (Lit != LitModifier::None) {
2459+
Inst.addOperand(
2460+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2461+
} else {
2462+
Inst.addOperand(MCOperand::createImm(Val));
2463+
}
24672464
return;
24682465
}
24692466

@@ -2483,12 +2480,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24832480
case AMDGPU::OPERAND_REG_IMM_V2INT32:
24842481
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
24852482
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
2486-
Inst.addOperand(MCOperand::createImm(Val));
2487-
return;
2483+
break;
24882484

24892485
case AMDGPU::OPERAND_REG_IMM_INT64:
24902486
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2491-
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2487+
if (Lit == LitModifier::None &&
2488+
AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
24922489
Inst.addOperand(MCOperand::createImm(Val));
24932490
return;
24942491
}
@@ -2499,19 +2496,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24992496
// LSBs.
25002497
if (!AsmParser->has64BitLiterals() || Lit == LitModifier::Lit)
25012498
Val = Lo_32(Val);
2502-
2503-
if (Lit != LitModifier::None) {
2504-
Inst.addOperand(
2505-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2506-
} else {
2507-
Inst.addOperand(MCOperand::createImm(Val));
2508-
}
2509-
return;
2499+
break;
25102500

25112501
case AMDGPU::OPERAND_REG_IMM_FP64:
25122502
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
25132503
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2514-
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2504+
if (Lit == LitModifier::None &&
2505+
AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
25152506
Inst.addOperand(MCOperand::createImm(Val));
25162507
return;
25172508
}
@@ -2534,14 +2525,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25342525
// For FP64 operands lit() specifies the high half of the value.
25352526
if (Lit == LitModifier::Lit)
25362527
Val = Hi_32(Val);
2537-
2538-
if (Lit != LitModifier::None) {
2539-
Inst.addOperand(
2540-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2541-
} else {
2542-
Inst.addOperand(MCOperand::createImm(Val));
2543-
}
2544-
return;
2528+
break;
25452529

25462530
case AMDGPU::OPERAND_REG_IMM_INT16:
25472531
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
@@ -2554,24 +2538,23 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25542538
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
25552539
case AMDGPU::OPERAND_KIMM32:
25562540
case AMDGPU::OPERAND_KIMM16:
2557-
Inst.addOperand(MCOperand::createImm(Val));
2558-
return;
2541+
break;
25592542

25602543
case AMDGPU::OPERAND_KIMM64:
25612544
if ((isInt<32>(Val) || isUInt<32>(Val)) && Lit != LitModifier::Lit64)
25622545
Val <<= 32;
2563-
2564-
if (Lit != LitModifier::None) {
2565-
Inst.addOperand(
2566-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2567-
} else {
2568-
Inst.addOperand(MCOperand::createImm(Val));
2569-
}
2570-
return;
2546+
break;
25712547

25722548
default:
25732549
llvm_unreachable("invalid operand type");
25742550
}
2551+
2552+
if (Lit != LitModifier::None) {
2553+
Inst.addOperand(
2554+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2555+
} else {
2556+
Inst.addOperand(MCOperand::createImm(Val));
2557+
}
25752558
}
25762559

25772560
void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,13 @@ void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
7373
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
7474
const MCSubtargetInfo &STI,
7575
raw_ostream &O) {
76-
O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
76+
const MCOperand &Op = MI->getOperand(OpNo);
77+
if (Op.isExpr()) {
78+
MAI.printExpr(O, *Op.getExpr());
79+
return;
80+
}
81+
82+
O << formatHex(Op.getImm() & 0xffffffff);
7783
}
7884

7985
void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -270,10 +270,19 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
270270
const MCInstrDesc &Desc, const MCOperand &MO, unsigned OpNo,
271271
const MCSubtargetInfo &STI, bool HasMandatoryLiteral) const {
272272
const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
273-
int64_t Imm;
273+
int64_t Imm = 0;
274274
if (MO.isExpr()) {
275-
if (!MO.getExpr()->evaluateAsAbsolute(Imm))
276-
return AMDGPU::getOperandSize(OpInfo) == 8 ? 254 : 255;
275+
if (!MO.getExpr()->evaluateAsAbsolute(Imm) ||
276+
AMDGPU::isLitExpr(MO.getExpr())) {
277+
if (OpInfo.OperandType == AMDGPU::OPERAND_KIMM16 ||
278+
OpInfo.OperandType == AMDGPU::OPERAND_KIMM32 ||
279+
OpInfo.OperandType == AMDGPU::OPERAND_KIMM64)
280+
return Imm;
281+
if (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
282+
AMDGPU::getOperandSize(OpInfo) == 8)
283+
return 254;
284+
return 255;
285+
}
277286
} else {
278287
assert(!MO.isDFPImm());
279288

‎llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,9 @@ s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678
6262
s_mov_b64 s[2:3], 0xffffffff01234567
6363
// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
6464

65+
// TODO: disasm
6566
s_mov_b64 s[2:3], lit64(0x777)
66-
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
67+
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xfe,0x01,0x82,0xbe,0x77,0x07,0x00,0x00,0x00,0x00,0x00,0x00]
6768
// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
6869

6970
s_mov_b64 s[2:3], 0x777

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