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[MLIR][ArmSVE] Add an ArmSVE dialect operation which maps to svdupq_lane (#135633)
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‎mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td‎

Lines changed: 66 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,13 @@ class Scalable1DVectorOfLength<int length, list<Type> elementTypes> : ShapedCont
6161
"a 1-D scalable vector with length " # length,
6262
"::mlir::VectorType">;
6363

64+
def SVEVector : AnyTypeOf<[
65+
Scalable1DVectorOfLength<2, [I64, F64]>,
66+
Scalable1DVectorOfLength<4, [I32, F32]>,
67+
Scalable1DVectorOfLength<8, [I16, F16, BF16]>,
68+
Scalable1DVectorOfLength<16, [I8]>],
69+
"an SVE vector with element size <= 64-bit">;
70+
6471
//===----------------------------------------------------------------------===//
6572
// ArmSVE op definitions
6673
//===----------------------------------------------------------------------===//
@@ -72,14 +79,22 @@ class ArmSVE_IntrOp<string mnemonic,
7279
list<Trait> traits = [],
7380
list<int> overloadedOperands = [],
7481
list<int> overloadedResults = [],
75-
int numResults = 1> :
82+
int numResults = 1,
83+
list<int> immArgPositions = [],
84+
list<string> immArgAttrNames = []> :
7685
LLVM_IntrOpBase</*Dialect dialect=*/ArmSVE_Dialect,
7786
/*string opName=*/"intr." # mnemonic,
7887
/*string enumName=*/"aarch64_sve_" # !subst(".", "_", mnemonic),
7988
/*list<int> overloadedResults=*/overloadedResults,
8089
/*list<int> overloadedOperands=*/overloadedOperands,
8190
/*list<Trait> traits=*/traits,
82-
/*int numResults=*/numResults>;
91+
/*int numResults=*/numResults,
92+
/*bit requiresAccessGroup=*/0,
93+
/*bit requiresAliasAnalysis=*/0,
94+
/*bit requiresFastmath=*/0,
95+
/*bit requiresOpBundles=*/0,
96+
/*list<int> immArgPositions=*/immArgPositions,
97+
/*list<string> immArgAttrNames=*/immArgAttrNames>;
8398

8499
class ArmSVE_IntrBinaryOverloadedOp<string mnemonic,
85100
list<Trait> traits = []>:
@@ -509,6 +524,45 @@ def ScalableMaskedUDivIOp : ScalableMaskedIOp<"masked.divi_unsigned",
509524

510525
def ScalableMaskedDivFOp : ScalableMaskedFOp<"masked.divf", "division">;
511526

527+
def DupQLaneOp : ArmSVE_Op<"dupq_lane", [Pure, AllTypesMatch<["src", "dst"]>]> {
528+
let summary = "Broadcast indexed 128-bit segment to vector";
529+
530+
let description = [{
531+
This operation fills each 128-bit segment of a vector with the elements
532+
from the indexed 128-bit segment of the source vector. If the VL is
533+
128 bits the operation is a NOP. If the index exceeds the number of
534+
128-bit segments in a vector the result is an all-zeroes vector.
535+
536+
Example:
537+
```mlir
538+
// VL == 256
539+
// %X = [A B C D x x x x]
540+
%Y = arm_sve.dupq_lane %X[0] : vector<[4]xi32>
541+
// Y = [A B C D A B C D]
542+
543+
// %U = [x x x x x x x x A B C D E F G H]
544+
%V = arm_sve.dupq_lane %U[1] : vector<[8]xf16>
545+
// %V = [A B C D E F H A B C D E F H]
546+
```
547+
548+
Note: The semantics of the operation match those of the `svdupq_lane` instrinsics.
549+
[Source](https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svdupq_lane)
550+
}];
551+
552+
let arguments = (ins SVEVector:$src,
553+
I64Attr:$lane);
554+
let results = (outs SVEVector:$dst);
555+
556+
let builders = [
557+
OpBuilder<(ins "Value":$src, "int64_t":$lane), [{
558+
build($_builder, $_state, src.getType(), src, lane);
559+
}]>];
560+
561+
let assemblyFormat = [{
562+
$src `[` $lane `]` attr-dict `:` type($dst)
563+
}];
564+
}
565+
512566
def UmmlaIntrOp :
513567
ArmSVE_IntrBinaryOverloadedOp<"ummla">,
514568
Arguments<(ins AnyScalableVectorOfAnyRank, AnyScalableVectorOfAnyRank, AnyScalableVectorOfAnyRank)>;
@@ -610,4 +664,14 @@ def WhileLTIntrOp :
610664
/*overloadedResults=*/[0]>,
611665
Arguments<(ins I64:$base, I64:$n)>;
612666

667+
def DupQLaneIntrOp : ArmSVE_IntrOp<"dupq_lane",
668+
/*traits=*/[],
669+
/*overloadedOperands=*/[0],
670+
/*overloadedResults=*/[],
671+
/*numResults=*/1,
672+
/*immArgPositions*/[1],
673+
/*immArgAttrNames*/["lane"]>,
674+
Arguments<(ins Arg<ScalableVectorOfRank<[1]>, "v">:$v,
675+
Arg<I64Attr, "lane">:$lane)>;
676+
613677
#endif // ARMSVE_OPS

‎mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp‎

Lines changed: 43 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@ using SdotOpLowering = OneToOneConvertToLLVMPattern<SdotOp, SdotIntrOp>;
2424
using SmmlaOpLowering = OneToOneConvertToLLVMPattern<SmmlaOp, SmmlaIntrOp>;
2525
using UdotOpLowering = OneToOneConvertToLLVMPattern<UdotOp, UdotIntrOp>;
2626
using UmmlaOpLowering = OneToOneConvertToLLVMPattern<UmmlaOp, UmmlaIntrOp>;
27+
using DupQLaneLowering =
28+
OneToOneConvertToLLVMPattern<DupQLaneOp, DupQLaneIntrOp>;
2729
using ScalableMaskedAddIOpLowering =
2830
OneToOneConvertToLLVMPattern<ScalableMaskedAddIOp,
2931
ScalableMaskedAddIIntrOp>;
@@ -188,24 +190,25 @@ void mlir::populateArmSVELegalizeForLLVMExportPatterns(
188190
// Populate conversion patterns
189191

190192
// clang-format off
191-
patterns.add<SdotOpLowering,
192-
SmmlaOpLowering,
193-
UdotOpLowering,
194-
UmmlaOpLowering,
195-
ScalableMaskedAddIOpLowering,
193+
patterns.add<ConvertFromSvboolOpLowering,
194+
ConvertToSvboolOpLowering,
195+
DupQLaneLowering,
196+
PselOpLowering,
196197
ScalableMaskedAddFOpLowering,
197-
ScalableMaskedSubIOpLowering,
198-
ScalableMaskedSubFOpLowering,
199-
ScalableMaskedMulIOpLowering,
198+
ScalableMaskedAddIOpLowering,
199+
ScalableMaskedDivFOpLowering,
200200
ScalableMaskedMulFOpLowering,
201+
ScalableMaskedMulIOpLowering,
201202
ScalableMaskedSDivIOpLowering,
203+
ScalableMaskedSubFOpLowering,
204+
ScalableMaskedSubIOpLowering,
202205
ScalableMaskedUDivIOpLowering,
203-
ScalableMaskedDivFOpLowering,
204-
ConvertToSvboolOpLowering,
205-
ConvertFromSvboolOpLowering,
206+
SmmlaOpLowering,
207+
UdotOpLowering,
208+
UmmlaOpLowering,
206209
ZipX2OpLowering,
207210
ZipX4OpLowering,
208-
PselOpLowering>(converter);
211+
SdotOpLowering>(converter);
209212
// Add vector.create_mask conversion with a high benefit as it produces much
210213
// nicer code than the generic lowering.
211214
patterns.add<CreateMaskOpLowering>(converter, /*benefit=*/4096);
@@ -215,41 +218,44 @@ void mlir::populateArmSVELegalizeForLLVMExportPatterns(
215218
void mlir::configureArmSVELegalizeForExportTarget(
216219
LLVMConversionTarget &target) {
217220
// clang-format off
218-
target.addLegalOp<SdotIntrOp,
219-
SmmlaIntrOp,
220-
UdotIntrOp,
221-
UmmlaIntrOp,
222-
ScalableMaskedAddIIntrOp,
221+
target.addLegalOp<ConvertFromSvboolIntrOp,
222+
ConvertToSvboolIntrOp,
223+
DupQLaneIntrOp,
224+
PselIntrOp,
223225
ScalableMaskedAddFIntrOp,
224-
ScalableMaskedSubIIntrOp,
225-
ScalableMaskedSubFIntrOp,
226-
ScalableMaskedMulIIntrOp,
226+
ScalableMaskedAddIIntrOp,
227+
ScalableMaskedDivFIntrOp,
227228
ScalableMaskedMulFIntrOp,
229+
ScalableMaskedMulIIntrOp,
228230
ScalableMaskedSDivIIntrOp,
231+
ScalableMaskedSubFIntrOp,
232+
ScalableMaskedSubIIntrOp,
229233
ScalableMaskedUDivIIntrOp,
230-
ScalableMaskedDivFIntrOp,
231-
ConvertToSvboolIntrOp,
232-
ConvertFromSvboolIntrOp,
234+
SmmlaIntrOp,
235+
UdotIntrOp,
236+
UmmlaIntrOp,
237+
WhileLTIntrOp,
233238
ZipX2IntrOp,
234239
ZipX4IntrOp,
235-
PselIntrOp,
236-
WhileLTIntrOp>();
237-
target.addIllegalOp<SdotOp,
238-
SmmlaOp,
239-
UdotOp,
240-
UmmlaOp,
241-
ScalableMaskedAddIOp,
240+
SdotIntrOp>();
241+
target.addIllegalOp<ConvertFromSvboolOp,
242+
ConvertToSvboolOp,
243+
DupQLaneOp,
244+
PselOp,
242245
ScalableMaskedAddFOp,
243-
ScalableMaskedSubIOp,
244-
ScalableMaskedSubFOp,
245-
ScalableMaskedMulIOp,
246+
ScalableMaskedAddIOp,
247+
ScalableMaskedDivFOp,
246248
ScalableMaskedMulFOp,
249+
ScalableMaskedMulIOp,
247250
ScalableMaskedSDivIOp,
251+
ScalableMaskedSubFOp,
252+
ScalableMaskedSubIOp,
248253
ScalableMaskedUDivIOp,
249-
ScalableMaskedDivFOp,
250-
ConvertToSvboolOp,
251-
ConvertFromSvboolOp,
254+
SmmlaOp,
255+
UdotOp,
256+
UmmlaOp,
252257
ZipX2Op,
253-
ZipX4Op>();
258+
ZipX4Op,
259+
SdotOp>();
254260
// clang-format on
255261
}

‎mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,3 +271,44 @@ func.func @arm_sve_psel_mixed_predicate_types(%p0: vector<[8]xi1>, %p1: vector<[
271271
%0 = arm_sve.psel %p0, %p1[%index] : vector<[8]xi1>, vector<[16]xi1>
272272
return %0 : vector<[8]xi1>
273273
}
274+
275+
// -----
276+
277+
// CHECK-LABEL: @arm_sve_dupq_lane(
278+
// CHECK-SAME: %[[A0:[a-z0-9]+]]: vector<[16]xi8>
279+
// CHECK-SAME: %[[A1:[a-z0-9]+]]: vector<[8]xi16>
280+
// CHECK-SAME: %[[A2:[a-z0-9]+]]: vector<[8]xf16>
281+
// CHECK-SAME: %[[A3:[a-z0-9]+]]: vector<[8]xbf16>
282+
// CHECK-SAME: %[[A4:[a-z0-9]+]]: vector<[4]xi32>
283+
// CHECK-SAME: %[[A5:[a-z0-9]+]]: vector<[4]xf32>
284+
// CHECK-SAME: %[[A6:[a-z0-9]+]]: vector<[2]xi64>
285+
// CHECK-SAME: %[[A7:[a-z0-9]+]]: vector<[2]xf64>
286+
// CHECK-SAME: -> !llvm.struct<(vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>, vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>)> {
287+
func.func @arm_sve_dupq_lane(
288+
%v16i8: vector<[16]xi8>, %v8i16: vector<[8]xi16>,
289+
%v8f16: vector<[8]xf16>, %v8bf16: vector<[8]xbf16>,
290+
%v4i32: vector<[4]xi32>, %v4f32: vector<[4]xf32>,
291+
%v2i64: vector<[2]xi64>, %v2f64: vector<[2]xf64>)
292+
-> (vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>,
293+
vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>) {
294+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A0]]) <{lane = 0 : i64}> : (vector<[16]xi8>) -> vector<[16]xi8>
295+
%0 = arm_sve.dupq_lane %v16i8[0] : vector<[16]xi8>
296+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A1]]) <{lane = 1 : i64}> : (vector<[8]xi16>) -> vector<[8]xi16>
297+
%1 = arm_sve.dupq_lane %v8i16[1] : vector<[8]xi16>
298+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A2]]) <{lane = 2 : i64}> : (vector<[8]xf16>) -> vector<[8]xf16>
299+
%2 = arm_sve.dupq_lane %v8f16[2] : vector<[8]xf16>
300+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A3]]) <{lane = 3 : i64}> : (vector<[8]xbf16>) -> vector<[8]xbf16>
301+
%3 = arm_sve.dupq_lane %v8bf16[3] : vector<[8]xbf16>
302+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A4]]) <{lane = 4 : i64}> : (vector<[4]xi32>) -> vector<[4]xi32>
303+
%4 = arm_sve.dupq_lane %v4i32[4] : vector<[4]xi32>
304+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A5]]) <{lane = 5 : i64}> : (vector<[4]xf32>) -> vector<[4]xf32>
305+
%5 = arm_sve.dupq_lane %v4f32[5] : vector<[4]xf32>
306+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A6]]) <{lane = 6 : i64}> : (vector<[2]xi64>) -> vector<[2]xi64>
307+
%6 = arm_sve.dupq_lane %v2i64[6] : vector<[2]xi64>
308+
// CHECK: "arm_sve.intr.dupq_lane"(%[[A7]]) <{lane = 7 : i64}> : (vector<[2]xf64>) -> vector<[2]xf64>
309+
%7 = arm_sve.dupq_lane %v2f64[7] : vector<[2]xf64>
310+
311+
return %0, %1, %2, %3, %4, %5, %6, %7
312+
: vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>,
313+
vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>
314+
}

‎mlir/test/Target/LLVMIR/arm-sve.mlir‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -390,3 +390,35 @@ llvm.func @arm_sve_psel(%pn: vector<[16]xi1>, %p1: vector<[2]xi1>, %p2: vector<[
390390
"arm_sve.intr.psel"(%pn, %p4, %index) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>
391391
llvm.return
392392
}
393+
394+
// CHECK-LABEL: @arm_sve_dupq_lane
395+
// CHECK-SAME: <vscale x 16 x i8> %[[V0:[0-9]+]]
396+
// CHECK-SAME: <vscale x 8 x i16> %[[V1:[0-9]+]]
397+
// CHECK-SAME: <vscale x 8 x half> %[[V2:[0-9]+]]
398+
// CHECK-SAME: <vscale x 8 x bfloat> %[[V3:[0-9]+]]
399+
// CHECK-SAME: <vscale x 4 x i32> %[[V4:[0-9]+]]
400+
// CHECK-SAME: <vscale x 4 x float> %[[V5:[0-9]+]]
401+
// CHECK-SAME: <vscale x 2 x i64> %[[V6:[0-9]+]]
402+
// CHECK-SAME: <vscale x 2 x double> %[[V7:[0-9]+]]
403+
llvm.func @arm_sve_dupq_lane(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>,
404+
%nxv8f16: vector<[8]xf16>, %nxv8bf16: vector<[8]xbf16>,
405+
%nxv4i32: vector<[4]xi32>, %nxv4f32: vector<[4]xf32>,
406+
%nxv2i64: vector<[2]xi64>, %nxv2f64: vector<[2]xf64>) {
407+
// CHECK: call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %[[V0]], i64 0)
408+
%0 = "arm_sve.intr.dupq_lane"(%nxv16i8) <{lane = 0 : i64}> : (vector<[16]xi8>) -> vector<[16]xi8>
409+
// CHECK: call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %[[V1]], i64 1)
410+
%1 = "arm_sve.intr.dupq_lane"(%nxv8i16) <{lane = 1 : i64}> : (vector<[8]xi16>) -> vector<[8]xi16>
411+
// CHECK: call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %[[V2]], i64 2)
412+
%2 = "arm_sve.intr.dupq_lane"(%nxv8f16) <{lane = 2 : i64}> : (vector<[8]xf16>) -> vector<[8]xf16>
413+
// CHECK: call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> %[[V3]], i64 3)
414+
%3 = "arm_sve.intr.dupq_lane"(%nxv8bf16) <{lane = 3 : i64}> : (vector<[8]xbf16>) -> vector<[8]xbf16>
415+
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %[[V4]], i64 4)
416+
%4 = "arm_sve.intr.dupq_lane"(%nxv4i32) <{lane = 4 : i64}> : (vector<[4]xi32>) -> vector<[4]xi32>
417+
// CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %[[V5]], i64 5)
418+
%5 = "arm_sve.intr.dupq_lane"(%nxv4f32) <{lane = 5 : i64}> : (vector<[4]xf32>) -> vector<[4]xf32>
419+
// CHECK: call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %[[V6]], i64 6)
420+
%6 = "arm_sve.intr.dupq_lane"(%nxv2i64) <{lane = 6 : i64}> : (vector<[2]xi64>) -> vector<[2]xi64>
421+
// CHECK: call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %[[V7]], i64 7)
422+
%7 = "arm_sve.intr.dupq_lane"(%nxv2f64) <{lane = 7 : i64}> : (vector<[2]xf64>) -> vector<[2]xf64>
423+
llvm.return
424+
}

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