Skip to content

Commit 63af232

Browse files
[LLVM][DAGCombiner] Improve simplifyDivRem's effectiveness after type legalisation.
simplifyDivRem does not work as well after type legalsiation because splatted constants can have a size mismatch between the scalar to splat and the element type of the splatted result. simplifyDivRem does not seem to care about this mismatch so I've updated the isConstOrConstSplat call for the divisor to allow truncation.
1 parent ff9cdbd commit 63af232

File tree

2 files changed

+86
-1
lines changed

2 files changed

+86
-1
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5042,7 +5042,7 @@ static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
50425042

50435043
unsigned Opc = N->getOpcode();
50445044
bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
5045-
ConstantSDNode *N1C = isConstOrConstSplat(N1);
5045+
ConstantSDNode *N1C = isConstOrConstSplat(N1, false, true);
50465046

50475047
// X / undef -> undef
50485048
// X % undef -> undef

llvm/test/CodeGen/AArch64/combine-sdiv.ll

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1774,3 +1774,88 @@ define i128 @combine_i128_sdiv_const100(i128 %x) {
17741774
%1 = sdiv i128 %x, 100
17751775
ret i128 %1
17761776
}
1777+
1778+
; The following only becomes an sdiv_by_one after type legalisation, after which
1779+
; the splatted scalar constant has a different type to the splat vector. This
1780+
; test verifies DAGCombiner does not care about this type difference.
1781+
define <16 x i16> @combine_vec_sdiv_by_one_obfuscated(<16 x i16> %x) "target-features"="+sve" {
1782+
; CHECK-SD-LABEL: combine_vec_sdiv_by_one_obfuscated:
1783+
; CHECK-SD: // %bb.0:
1784+
; CHECK-SD-NEXT: ret
1785+
;
1786+
; CHECK-GI-LABEL: combine_vec_sdiv_by_one_obfuscated:
1787+
; CHECK-GI: // %bb.0:
1788+
; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
1789+
; CHECK-GI-NEXT: movi v3.8h, #1
1790+
; CHECK-GI-NEXT: smov w8, v0.h[0]
1791+
; CHECK-GI-NEXT: mov v3.h[0], v2.h[0]
1792+
; CHECK-GI-NEXT: smov w9, v3.h[0]
1793+
; CHECK-GI-NEXT: smov w16, v3.h[7]
1794+
; CHECK-GI-NEXT: sdiv w14, w8, w9
1795+
; CHECK-GI-NEXT: smov w8, v0.h[1]
1796+
; CHECK-GI-NEXT: smov w9, v3.h[1]
1797+
; CHECK-GI-NEXT: sdiv w15, w8, w9
1798+
; CHECK-GI-NEXT: smov w8, v0.h[2]
1799+
; CHECK-GI-NEXT: smov w9, v3.h[2]
1800+
; CHECK-GI-NEXT: sdiv w13, w8, w9
1801+
; CHECK-GI-NEXT: smov w8, v0.h[3]
1802+
; CHECK-GI-NEXT: smov w9, v3.h[3]
1803+
; CHECK-GI-NEXT: sdiv w12, w8, w9
1804+
; CHECK-GI-NEXT: smov w8, v0.h[4]
1805+
; CHECK-GI-NEXT: smov w9, v3.h[4]
1806+
; CHECK-GI-NEXT: sdiv w11, w8, w9
1807+
; CHECK-GI-NEXT: smov w8, v0.h[5]
1808+
; CHECK-GI-NEXT: smov w9, v3.h[5]
1809+
; CHECK-GI-NEXT: sdiv w10, w8, w9
1810+
; CHECK-GI-NEXT: smov w8, v0.h[6]
1811+
; CHECK-GI-NEXT: smov w9, v3.h[6]
1812+
; CHECK-GI-NEXT: movi v3.8h, #1
1813+
; CHECK-GI-NEXT: smov w17, v3.h[0]
1814+
; CHECK-GI-NEXT: smov w18, v3.h[1]
1815+
; CHECK-GI-NEXT: smov w0, v3.h[2]
1816+
; CHECK-GI-NEXT: smov w1, v3.h[3]
1817+
; CHECK-GI-NEXT: smov w2, v3.h[4]
1818+
; CHECK-GI-NEXT: smov w3, v3.h[5]
1819+
; CHECK-GI-NEXT: sdiv w8, w8, w9
1820+
; CHECK-GI-NEXT: smov w9, v0.h[7]
1821+
; CHECK-GI-NEXT: fmov s0, w14
1822+
; CHECK-GI-NEXT: mov v0.h[1], w15
1823+
; CHECK-GI-NEXT: smov w15, v1.h[6]
1824+
; CHECK-GI-NEXT: mov v0.h[2], w13
1825+
; CHECK-GI-NEXT: sdiv w9, w9, w16
1826+
; CHECK-GI-NEXT: smov w16, v1.h[0]
1827+
; CHECK-GI-NEXT: mov v0.h[3], w12
1828+
; CHECK-GI-NEXT: smov w12, v1.h[7]
1829+
; CHECK-GI-NEXT: mov v0.h[4], w11
1830+
; CHECK-GI-NEXT: sdiv w16, w16, w17
1831+
; CHECK-GI-NEXT: smov w17, v1.h[1]
1832+
; CHECK-GI-NEXT: mov v0.h[5], w10
1833+
; CHECK-GI-NEXT: mov v0.h[6], w8
1834+
; CHECK-GI-NEXT: sdiv w17, w17, w18
1835+
; CHECK-GI-NEXT: smov w18, v1.h[2]
1836+
; CHECK-GI-NEXT: fmov s2, w16
1837+
; CHECK-GI-NEXT: smov w16, v3.h[6]
1838+
; CHECK-GI-NEXT: mov v0.h[7], w9
1839+
; CHECK-GI-NEXT: sdiv w18, w18, w0
1840+
; CHECK-GI-NEXT: smov w0, v1.h[3]
1841+
; CHECK-GI-NEXT: mov v2.h[1], w17
1842+
; CHECK-GI-NEXT: sdiv w0, w0, w1
1843+
; CHECK-GI-NEXT: smov w1, v1.h[4]
1844+
; CHECK-GI-NEXT: mov v2.h[2], w18
1845+
; CHECK-GI-NEXT: sdiv w1, w1, w2
1846+
; CHECK-GI-NEXT: smov w2, v1.h[5]
1847+
; CHECK-GI-NEXT: mov v2.h[3], w0
1848+
; CHECK-GI-NEXT: sdiv w14, w2, w3
1849+
; CHECK-GI-NEXT: mov v2.h[4], w1
1850+
; CHECK-GI-NEXT: sdiv w13, w15, w16
1851+
; CHECK-GI-NEXT: smov w15, v3.h[7]
1852+
; CHECK-GI-NEXT: mov v2.h[5], w14
1853+
; CHECK-GI-NEXT: sdiv w10, w12, w15
1854+
; CHECK-GI-NEXT: mov v2.h[6], w13
1855+
; CHECK-GI-NEXT: mov v2.h[7], w10
1856+
; CHECK-GI-NEXT: mov v1.16b, v2.16b
1857+
; CHECK-GI-NEXT: ret
1858+
%1 = shufflevector <16 x i16> zeroinitializer, <16 x i16> splat (i16 1), <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1859+
%2 = sdiv <16 x i16> %x, %1
1860+
ret <16 x i16> %2
1861+
}

0 commit comments

Comments
 (0)