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Simpliy handling for spilling of acc reg with stx by removing
explicit register arithmetic and clean up code gen for register mapping used in stxvp spilling.
1 parent 4681ce5 commit 63c233d

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2 files changed

+47
-46
lines changed

2 files changed

+47
-46
lines changed

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 42 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1238,40 +1238,28 @@ static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
12381238
#endif
12391239
}
12401240

1241-
static void spillRegPairs(MachineBasicBlock &MBB,
1242-
MachineBasicBlock::iterator II, DebugLoc DL,
1243-
const TargetInstrInfo &TII, Register SrcReg,
1244-
unsigned FrameIndex, bool IsLittleEndian,
1245-
bool IsKilled, bool TwoPairs) {
1246-
unsigned Offset = 0;
1247-
// The register arithmetic in this function does not support virtual
1248-
// registers.
1249-
assert(!SrcReg.isVirtual() &&
1241+
void PPCRegisterInfo::spillRegPair(MachineBasicBlock &MBB,
1242+
MachineBasicBlock::iterator II, DebugLoc DL,
1243+
const TargetInstrInfo &TII,
1244+
unsigned FrameIndex, bool IsLittleEndian,
1245+
bool IsKilled, Register Reg,
1246+
int Offset) const {
1247+
1248+
// This function does not support virtual registers.
1249+
assert(!Reg.isVirtual() &&
12501250
"Spilling register pairs does not support virtual registers.");
12511251

1252-
if (TwoPairs)
1253-
Offset = IsLittleEndian ? 48 : 0;
1254-
else
1255-
Offset = IsLittleEndian ? 16 : 0;
1256-
Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2
1257-
: PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1258-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1259-
.addReg(Reg, getKillRegState(IsKilled)),
1260-
FrameIndex, Offset);
1261-
Offset += IsLittleEndian ? -16 : 16;
1262-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1263-
.addReg(Reg + 1, getKillRegState(IsKilled)),
1264-
FrameIndex, Offset);
1265-
if (TwoPairs) {
1266-
Offset += IsLittleEndian ? -16 : 16;
1267-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1268-
.addReg(Reg + 2, getKillRegState(IsKilled)),
1269-
FrameIndex, Offset);
1270-
Offset += IsLittleEndian ? -16 : 16;
1271-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1272-
.addReg(Reg + 3, getKillRegState(IsKilled)),
1273-
FrameIndex, Offset);
1274-
}
1252+
addFrameReference(
1253+
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1254+
.addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx0),
1255+
getKillRegState(IsKilled)),
1256+
FrameIndex, Offset);
1257+
1258+
addFrameReference(
1259+
BuildMI(MBB, II, DL, TII.get(PPC::STXV))
1260+
.addReg(TargetRegisterInfo::getSubReg(Reg, PPC::sub_vsx1),
1261+
getKillRegState(IsKilled)),
1262+
FrameIndex, IsLittleEndian ? Offset - 16 : Offset + 16);
12751263
}
12761264

12771265
/// Remove any STXVP[X] instructions and split them out into a pair of
@@ -1290,8 +1278,10 @@ void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
12901278
Register SrcReg = MI.getOperand(0).getReg();
12911279
bool IsLittleEndian = Subtarget.isLittleEndian();
12921280
bool IsKilled = MI.getOperand(0).isKill();
1293-
spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled,
1294-
/* TwoPairs */ false);
1281+
1282+
spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, SrcReg,
1283+
IsLittleEndian ? 16 : 0);
1284+
12951285
// Discard the original instruction.
12961286
MBB.erase(II);
12971287
}
@@ -1325,8 +1315,6 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
13251315
bool IsKilled = MI.getOperand(0).isKill();
13261316

13271317
bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1328-
Register Reg =
1329-
PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
13301318
bool IsLittleEndian = Subtarget.isLittleEndian();
13311319

13321320
emitAccSpillRestoreInfo(MBB, IsPrimed, false);
@@ -1337,16 +1325,24 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
13371325
// adjust the offset of the store that is within the 64-byte stack slot.
13381326
if (IsPrimed)
13391327
BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1340-
if (DisableAutoPairedVecSt)
1341-
spillRegPairs(MBB, II, DL, TII, Reg, FrameIndex, IsLittleEndian, IsKilled,
1342-
/* TwoPairs */ true);
1343-
else {
1344-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1345-
.addReg(Reg, getKillRegState(IsKilled)),
1346-
FrameIndex, IsLittleEndian ? 32 : 0);
1347-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1348-
.addReg(Reg + 1, getKillRegState(IsKilled)),
1349-
FrameIndex, IsLittleEndian ? 0 : 32);
1328+
if (DisableAutoPairedVecSt) {
1329+
spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1330+
TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
1331+
IsLittleEndian ? 48 : 0);
1332+
spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1333+
TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
1334+
IsLittleEndian ? 16 : 32);
1335+
} else {
1336+
addFrameReference(
1337+
BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1338+
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0),
1339+
getKillRegState(IsKilled)),
1340+
FrameIndex, IsLittleEndian ? 32 : 0);
1341+
addFrameReference(
1342+
BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1343+
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair1),
1344+
getKillRegState(IsKilled)),
1345+
FrameIndex, IsLittleEndian ? 0 : 32);
13501346
}
13511347
if (IsPrimed && !IsKilled)
13521348
BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,11 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
5858
DenseMap<unsigned, unsigned> ImmToIdxMap;
5959
const PPCTargetMachine &TM;
6060

61+
void spillRegPair(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
62+
DebugLoc DL, const TargetInstrInfo &TII,
63+
unsigned FrameIndex, bool IsLittleEndian, bool IsKilled,
64+
Register Reg, int Offset) const;
65+
6166
public:
6267
PPCRegisterInfo(const PPCTargetMachine &TM);
6368

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