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1 parent 762f05d commit 643602eCopy full SHA for 643602e
llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
@@ -49,7 +49,7 @@ define <vscale x 16 x i8> @bfcvt(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloa
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; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: bfcvt z0.b, { z0.h, z1.h }
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; CHECK-NEXT: ret
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- %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
+ %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
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ret <vscale x 16 x i8> %res
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}
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