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[PPC] Implement BCD assist builtins (#101390)
Implement BCD assist builtins for XL and GCC compatibility. GCC compat: ``` unsigned int __builtin_cdtbcd (unsigned int); unsigned int __builtin_cbcdtd (unsigned int); unsigned int __builtin_addg6s (unsigned int, unsigned int); ``` 64BIT XL compat: ``` long long __cdtbcd (long long); long long __cbcdtd (long long); long long __addg6s (long long source1, long long source2) ```
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‎clang/include/clang/Basic/BuiltinsPPC.def‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector")
515515
TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
516516
TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
517517

518+
// P7 BCD builtins.
519+
TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
520+
TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
521+
TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions")
522+
523+
// P7 XL Compat BCD builtins.
524+
TARGET_BUILTIN(__builtin_ppc_cdtbcd, "LLiLLi", "", "isa-v206-instructions")
525+
TARGET_BUILTIN(__builtin_ppc_cbcdtd, "LLiLLi", "", "isa-v206-instructions")
526+
TARGET_BUILTIN(__builtin_ppc_addg6s, "LLiLLiLLi", "", "isa-v206-instructions")
527+
518528
// P8 BCD builtins.
519529
TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "",
520530
"isa-v207-instructions")

‎clang/lib/Basic/Targets/PPC.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,9 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
105105
}
106106

107107
static void defineXLCompatMacros(MacroBuilder &Builder) {
108+
Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
109+
Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
110+
Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
108111
Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
109112
Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
110113
Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");

‎clang/lib/Sema/SemaPPC.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,9 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
6161
case PPC::BI__builtin_bpermd:
6262
case PPC::BI__builtin_pdepd:
6363
case PPC::BI__builtin_pextd:
64+
case PPC::BI__builtin_ppc_cdtbcd:
65+
case PPC::BI__builtin_ppc_cbcdtd:
66+
case PPC::BI__builtin_ppc_addg6s:
6467
case PPC::BI__builtin_ppc_ldarx:
6568
case PPC::BI__builtin_ppc_stdcx:
6669
case PPC::BI__builtin_ppc_tdw:

‎clang/test/CodeGen/PowerPC/builtins-bcd-assist.c‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2+
// REQUIRES: powerpc-registered-target
3+
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
4+
// RUN: -emit-llvm %s -o - | FileCheck %s
5+
// RUN: %clang_cc1 -triple powerpc64-unknown-aix -O2 -target-cpu pwr7 \
6+
// RUN: -emit-llvm %s -o - | FileCheck %s
7+
// RUN: %clang_cc1 -triple powerpc-unknown-aix -O2 -target-cpu pwr7 \
8+
// RUN: -emit-llvm %s -o - | FileCheck %s
9+
10+
// CHECK-LABEL: define{{.*}} i64 @cdtbcd_test(i64
11+
// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
12+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32 [[CONV]])
13+
// CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[TMP0]] to i64
14+
// CHECK-NEXT: ret i64 [[CONV1]]
15+
long long cdtbcd_test(long long ll) {
16+
return __builtin_cdtbcd (ll);
17+
}
18+
19+
// CHECK-LABEL: define{{.*}} i32 @cdtbcd_test_ui(i32
20+
// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32
21+
// CHECK-NEXT: ret i32 [[TMP0]]
22+
unsigned int cdtbcd_test_ui(unsigned int ui) {
23+
return __builtin_cdtbcd (ui);
24+
}
25+
26+
// CHECK-LABEL: define{{.*}} i64 @cbcdtd_test(i64
27+
// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
28+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cbcdtd(i32 [[CONV]])
29+
// CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[TMP0]] to i64
30+
// CHECK-NEXT: ret i64 [[CONV1]]
31+
long long cbcdtd_test(long long ll) {
32+
return __builtin_cbcdtd (ll);
33+
}
34+
35+
// CHECK-LABEL: define{{.*}} i32 @cbcdtd_test_ui(i32
36+
// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cbcdtd(i32
37+
// CHECK-NEXT: ret i32 [[TMP0]]
38+
unsigned int cbcdtd_test_ui(unsigned int ui) {
39+
return __builtin_cbcdtd (ui);
40+
}
41+
42+
// CHECK-LABEL: define{{.*}} i64 @addg6s_test(i64
43+
// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
44+
// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 {{.*}} to i32
45+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.ppc.addg6s(i32 [[CONV]], i32 [[CONV1]])
46+
// CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[TMP0]] to i64
47+
// CHECK-NEXT: ret i64 [[CONV2]]
48+
//
49+
long long addg6s_test(long long ll, long long ll2) {
50+
return __builtin_addg6s (ll, ll2);
51+
}
52+
53+
// CHECK-LABEL: define{{.*}} i32 @addg6s_test_ui(i32
54+
// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.addg6s(i32 {{.*}}, i32
55+
// CHECK-NEXT: ret i32 [[TMP0]]
56+
unsigned int addg6s_test_ui(unsigned int ui, unsigned int ui2) {
57+
return __builtin_addg6s (ui, ui2);
58+
}

‎clang/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.c‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2+
// REQUIRES: powerpc-registered-target
3+
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
4+
// RUN: -emit-llvm %s -o - | FileCheck %s
5+
// RUN: %clang_cc1 -triple powerpc64-unknown-aix -O2 -target-cpu pwr7 \
6+
// RUN: -emit-llvm %s -o - | FileCheck %s
7+
// RUN: not %clang_cc1 -triple powerpc-unknown-aix -O2 -target-cpu pwr7 \
8+
// RUN: -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
9+
10+
// CHECK-LABEL: define{{.*}} i64 @cdtbcd_test(i64
11+
// CHECK-NEXT: [[ENTRY:.*:]]
12+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.cdtbcdd(i64
13+
// CHECK-NEXT: ret i64 [[TMP0]]
14+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
15+
// CHECK-32-ERROR: #define __cdtbcd __builtin_ppc_cdtbcd
16+
long long cdtbcd_test(long long ll) {
17+
return __cdtbcd (ll);
18+
}
19+
20+
// CHECK-LABEL: define{{.*}} i32 @cdtbcd_test_ui(i32
21+
// CHECK-NEXT: [[ENTRY:.*:]]
22+
// CHECK-NEXT: [[CONV:%.*]] = zext i32 {{.*}} to i64
23+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.cdtbcdd(i64 [[CONV]])
24+
// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
25+
// CHECK-NEXT: ret i32 [[CONV1]]
26+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
27+
// CHECK-32-ERROR: #define __cdtbcd __builtin_ppc_cdtbcd
28+
unsigned int cdtbcd_test_ui(unsigned int ui) {
29+
return __cdtbcd (ui);
30+
}
31+
32+
// CHECK-LABEL: define{{.*}} i64 @cbcdtd_test(i64
33+
// CHECK-NEXT: [[ENTRY:.*:]]
34+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.cbcdtdd(i64
35+
// CHECK-NEXT: ret i64 [[TMP0]]
36+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
37+
// CHECK-32-ERROR: #define __cbcdtd __builtin_ppc_cbcdtd
38+
long long cbcdtd_test(long long ll) {
39+
return __cbcdtd (ll);
40+
}
41+
42+
// CHECK-LABEL: define{{.*}} i32 @cbcdtd_test_ui(i32
43+
// CHECK-NEXT: [[ENTRY:.*:]]
44+
// CHECK-NEXT: [[CONV:%.*]] = zext i32 {{.*}} to i64
45+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.cbcdtdd(i64 [[CONV]])
46+
// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP0]] to i32
47+
// CHECK-NEXT: ret i32 [[CONV1]]
48+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
49+
// CHECK-32-ERROR: #define __cbcdtd __builtin_ppc_cbcdtd
50+
unsigned int cbcdtd_test_ui(unsigned int ui) {
51+
return __cbcdtd (ui);
52+
}
53+
54+
// CHECK-LABEL: define{{.*}} i64 @addg6s_test(i64
55+
// CHECK-NEXT: [[ENTRY:.*:]]
56+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.addg6sd(i64 {{.*}}, i64 {{.*}})
57+
// CHECK-NEXT: ret i64 [[TMP0]]
58+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
59+
// CHECK-32-ERROR: #define __addg6s __builtin_ppc_addg6s
60+
long long addg6s_test(long long ll, long long ll2) {
61+
return __addg6s (ll, ll2);
62+
}
63+
64+
// CHECK-LABEL: define{{.*}} i32 @addg6s_test_ui(i32
65+
// CHECK-NEXT: [[ENTRY:.*:]]
66+
// CHECK-NEXT: [[CONV:%.*]] = zext i32 {{.*}} to i64
67+
// CHECK-NEXT: [[CONV1:%.*]] = zext i32 {{.*}} to i64
68+
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.ppc.addg6sd(i64 {{.*}}, i64
69+
// CHECK-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP0]] to i32
70+
// CHECK-NEXT: ret i32 [[CONV2]]
71+
// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
72+
// CHECK-32-ERROR: #define __addg6s __builtin_ppc_addg6s
73+
unsigned int addg6s_test_ui(unsigned int ui, unsigned int ui2) {
74+
return __addg6s (ui, ui2);
75+
}

‎llvm/include/llvm/IR/IntrinsicsPowerPC.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -632,6 +632,19 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
632632
DefaultAttrsIntrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
633633

634634
// BCD intrinsics.
635+
def int_ppc_cdtbcdd : ClangBuiltin<"__builtin_ppc_cdtbcd">,
636+
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
637+
def int_ppc_cbcdtdd: ClangBuiltin<"__builtin_ppc_cbcdtd">,
638+
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
639+
def int_ppc_addg6sd: ClangBuiltin<"__builtin_ppc_addg6s">,
640+
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
641+
def int_ppc_cdtbcd : ClangBuiltin<"__builtin_cdtbcd">,
642+
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
643+
def int_ppc_cbcdtd: ClangBuiltin<"__builtin_cbcdtd">,
644+
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
645+
def int_ppc_addg6s: ClangBuiltin<"__builtin_addg6s">,
646+
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
647+
635648
def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">,
636649
DefaultAttrsIntrinsic<
637650
[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1014,12 +1014,14 @@ def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),
10141014
[(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;
10151015

10161016
def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST),
1017-
"cdtbcd $RA, $RST", IIC_IntGeneral, []>;
1017+
"cdtbcd $RA, $RST", IIC_IntGeneral,
1018+
[(set i64:$RA, (int_ppc_cdtbcdd i64:$RST))]>;
10181019
def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST),
1019-
"cbcdtd $RA, $RST", IIC_IntGeneral, []>;
1020-
1020+
"cbcdtd $RA, $RST", IIC_IntGeneral,
1021+
[(set i64:$RA, (int_ppc_cbcdtdd i64:$RST))]>;
10211022
def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1022-
"addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
1023+
"addg6s $RT, $RA, $RB", IIC_IntGeneral,
1024+
[(set i64:$RT, (int_ppc_addg6sd i64:$RA, i64:$RB))]>;
10231025
}
10241026

10251027
defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1931,12 +1931,14 @@ def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),
19311931
[(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;
19321932

19331933
def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST),
1934-
"cdtbcd $RA, $RST", IIC_IntGeneral, []>;
1934+
"cdtbcd $RA, $RST", IIC_IntGeneral,
1935+
[(set i32:$RA, (int_ppc_cdtbcd i32:$RST))]>;
19351936
def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST),
1936-
"cbcdtd $RA, $RST", IIC_IntGeneral, []>;
1937-
1937+
"cbcdtd $RA, $RST", IIC_IntGeneral,
1938+
[(set i32:$RA, (int_ppc_cbcdtd i32:$RST))]>;
19381939
def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
1939-
"addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
1940+
"addg6s $RT, $RA, $RB", IIC_IntGeneral,
1941+
[(set i32:$RT, (int_ppc_addg6s i32:$RA, i32:$RB))]>;
19401942

19411943
//===----------------------------------------------------------------------===//
19421944
// PPC32 Load Instructions.

‎llvm/test/CodeGen/PowerPC/builtins-bcd-assist.ll‎

Lines changed: 111 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,111 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \
3+
; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
4+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
5+
; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
6+
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
7+
; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX32
8+
9+
define dso_local i64 @cdtbcd_test(i64 noundef %ll) {
10+
; CHECK-LABEL: cdtbcd_test:
11+
; CHECK: # %bb.0: # %entry
12+
; CHECK-NEXT: cdtbcd r3, r3
13+
; CHECK-NEXT: clrldi r3, r3, 32
14+
; CHECK-NEXT: blr
15+
; CHECK-AIX32-LABEL: cdtbcd_test:
16+
; CHECK-AIX32: # %bb.0: # %entry
17+
; CHECK-AIX32-NEXT: li r3, 0
18+
; CHECK-AIX32-NEXT: cdtbcd r4, r4
19+
; CHECK-AIX32-NEXT: blr
20+
entry:
21+
%conv = trunc i64 %ll to i32
22+
%0 = tail call i32 @llvm.ppc.cdtbcd(i32 %conv)
23+
%conv1 = zext i32 %0 to i64
24+
ret i64 %conv1
25+
}
26+
27+
define dso_local zeroext i32 @cdtbcd_test_ui(i32 noundef zeroext %ui) {
28+
; CHECK-LABEL: cdtbcd_test_ui:
29+
; CHECK: # %bb.0: # %entry
30+
; CHECK-NEXT: cdtbcd r3, r3
31+
; CHECK-NEXT: clrldi r3, r3, 32
32+
; CHECK-NEXT: blr
33+
; CHECK-AIX32-LABEL: cdtbcd_test_ui:
34+
; CHECK-AIX32: # %bb.0: # %entry
35+
; CHECK-AIX32-NEXT: cdtbcd r3, r3
36+
; CHECK-AIX32-NEXT: blr
37+
entry:
38+
%0 = tail call i32 @llvm.ppc.cdtbcd(i32 %ui)
39+
ret i32 %0
40+
}
41+
42+
define dso_local i64 @cbcdtd_test(i64 noundef %ll) {
43+
; CHECK-LABEL: cbcdtd_test:
44+
; CHECK: # %bb.0: # %entry
45+
; CHECK-NEXT: cbcdtd r3, r3
46+
; CHECK-NEXT: clrldi r3, r3, 32
47+
; CHECK-NEXT: blr
48+
; CHECK-AIX32-LABEL: cbcdtd_test:
49+
; CHECK-AIX32: # %bb.0: # %entry
50+
; CHECK-AIX32-NEXT: li r3, 0
51+
; CHECK-AIX32-NEXT: cbcdtd r4, r4
52+
; CHECK-AIX32-NEXT: blr
53+
entry:
54+
%conv = trunc i64 %ll to i32
55+
%0 = tail call i32@llvm.ppc.cbcdtd(i32 %conv)
56+
%conv1 = zext i32 %0 to i64
57+
ret i64 %conv1
58+
}
59+
60+
define dso_local zeroext i32 @cbcdtd_test_ui(i32 noundef zeroext %ui) {
61+
; CHECK-LABEL: cbcdtd_test_ui:
62+
; CHECK: # %bb.0: # %entry
63+
; CHECK-NEXT: cbcdtd r3, r3
64+
; CHECK-NEXT: clrldi r3, r3, 32
65+
; CHECK-NEXT: blr
66+
; CHECK-AIX32-LABEL: cbcdtd_test_ui:
67+
; CHECK-AIX32: # %bb.0: # %entry
68+
; CHECK-AIX32-NEXT: cbcdtd r3, r3
69+
; CHECK-AIX32-NEXT: blr
70+
entry:
71+
%0 = tail call i32 @llvm.ppc.cbcdtd(i32 %ui)
72+
ret i32 %0
73+
}
74+
75+
define dso_local i64 @addg6s_test(i64 noundef %ll, i64 noundef %ll2) {
76+
; CHECK-LABEL: addg6s_test:
77+
; CHECK: bb.0: # %entry
78+
; CHECK-NEXT: addg6s r3, r3, r4
79+
; CHECK-NEXT: clrldi r3, r3, 32
80+
; CHECK-NEXT: blr
81+
; CHECK-AIX32-LABEL: addg6s_test:
82+
; CHECK-AIX32: # %bb.0: # %entry
83+
; CHECK-AIX32-NEXT: li r3, 0
84+
; CHECK-AIX32-NEXT: addg6s r4, r4, r6
85+
; CHECK-AIX32-NEXT: blr
86+
entry:
87+
%conv = trunc i64 %ll to i32
88+
%conv1 = trunc i64 %ll2 to i32
89+
%0 = tail call i32 @llvm.ppc.addg6s(i32 %conv, i32 %conv1)
90+
%conv2 = zext i32 %0 to i64
91+
ret i64 %conv2
92+
}
93+
94+
define dso_local zeroext i32 @addg6s_test_ui(i32 noundef zeroext %ui, i32 noundef zeroext %ui2) {
95+
; CHECK-LABEL: addg6s_test_ui:
96+
; CHECK: # %bb.0: # %entry
97+
; CHECK-NEXT: addg6s r3, r3, r4
98+
; CHECK-NEXT: clrldi r3, r3, 32
99+
; CHECK-NEXT: blr
100+
; CHECK-AIX32-LABEL: addg6s_test_ui:
101+
; CHECK-AIX32: # %bb.0: # %entry
102+
; CHECK-AIX32-NEXT: addg6s r3, r3, r4
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; CHECK-AIX32-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.addg6s(i32 %ui, i32 %ui2)
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ret i32 %0
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}
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declare i32 @llvm.ppc.cdtbcd(i32)
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declare i32 @llvm.ppc.cbcdtd(i32)
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declare i32 @llvm.ppc.addg6s(i32, i32)

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