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[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM
1 parent 8c58562 commit 646d2d1

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7 files changed

+124
-29
lines changed

7 files changed

+124
-29
lines changed

‎llvm/include/llvm/Passes/MachinePassRegistry.def‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
9696
// computed. (We still either need to regenerate kill flags after regalloc, or
9797
// preferably fix the scavenger to not depend on them).
9898
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
99+
MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis())
99100
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
100101
MACHINE_FUNCTION_ANALYSIS("machine-block-freq", MachineBlockFrequencyAnalysis())
101102
MACHINE_FUNCTION_ANALYSIS("machine-branch-prob",
@@ -122,8 +123,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis())
122123
// MachineRegionInfoPassAnalysis())
123124
// MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics",
124125
// MachineTraceMetricsAnalysis()) MACHINE_FUNCTION_ANALYSIS("reaching-def",
125-
// ReachingDefAnalysisAnalysis()) MACHINE_FUNCTION_ANALYSIS("live-reg-matrix",
126-
// LiveRegMatrixAnalysis()) MACHINE_FUNCTION_ANALYSIS("gc-analysis",
126+
// ReachingDefAnalysisAnalysis()) MACHINE_FUNCTION_ANALYSIS("gc-analysis",
127127
// GCMachineCodeAnalysisPass())
128128
#undef MACHINE_FUNCTION_ANALYSIS
129129

‎llvm/lib/Target/AMDGPU/AMDGPU.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ FunctionPass *createSIFixSGPRCopiesLegacyPass();
4949
FunctionPass *createLowerWWMCopiesPass();
5050
FunctionPass *createSIMemoryLegalizerPass();
5151
FunctionPass *createSIInsertWaitcntsPass();
52-
FunctionPass *createSIPreAllocateWWMRegsPass();
52+
FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
5353
FunctionPass *createSIFormMemoryClausesPass();
5454

5555
FunctionPass *createSIPostRABundlerPass();
@@ -208,8 +208,8 @@ extern char &SILateBranchLoweringPassID;
208208
void initializeSIOptimizeExecMaskingPass(PassRegistry &);
209209
extern char &SIOptimizeExecMaskingID;
210210

211-
void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
212-
extern char &SIPreAllocateWWMRegsID;
211+
void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
212+
extern char &SIPreAllocateWWMRegsLegacyID;
213213

214214
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
215215
extern char &AMDGPUImageIntrinsicOptimizerID;

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -461,7 +461,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
461461
initializeSILateBranchLoweringPass(*PR);
462462
initializeSIMemoryLegalizerPass(*PR);
463463
initializeSIOptimizeExecMaskingPass(*PR);
464-
initializeSIPreAllocateWWMRegsPass(*PR);
464+
initializeSIPreAllocateWWMRegsLegacyPass(*PR);
465465
initializeSIFormMemoryClausesPass(*PR);
466466
initializeSIPostRABundlerPass(*PR);
467467
initializeGCNCreateVOPDPass(*PR);
@@ -1443,7 +1443,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
14431443

14441444
// Equivalent of PEI for SGPRs.
14451445
addPass(&SILowerSGPRSpillsLegacyID);
1446-
addPass(&SIPreAllocateWWMRegsID);
1446+
addPass(&SIPreAllocateWWMRegsLegacyID);
14471447

14481448
addPass(createVGPRAllocPass(false));
14491449

@@ -1467,7 +1467,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
14671467

14681468
// Equivalent of PEI for SGPRs.
14691469
addPass(&SILowerSGPRSpillsLegacyID);
1470-
addPass(&SIPreAllocateWWMRegsID);
1470+
addPass(&SIPreAllocateWWMRegsLegacyID);
14711471

14721472
addPass(createVGPRAllocPass(true));
14731473

‎llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp‎

Lines changed: 39 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313

14+
#include "SIPreAllocateWWMRegs.h"
1415
#include "AMDGPU.h"
1516
#include "GCNSubtarget.h"
1617
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -34,7 +35,7 @@ static cl::opt<bool>
3435

3536
namespace {
3637

37-
class SIPreAllocateWWMRegs : public MachineFunctionPass {
38+
class SIPreAllocateWWMRegs {
3839
private:
3940
const SIInstrInfo *TII;
4041
const SIRegisterInfo *TRI;
@@ -48,13 +49,21 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
4849
#ifndef NDEBUG
4950
void printWWMInfo(const MachineInstr &MI);
5051
#endif
52+
bool processDef(MachineOperand &MO);
53+
void rewriteRegs(MachineFunction &MF);
54+
55+
public:
56+
SIPreAllocateWWMRegs(LiveIntervals *LIS, LiveRegMatrix *Matrix,
57+
VirtRegMap *VRM)
58+
: LIS(LIS), Matrix(Matrix), VRM(VRM) {}
59+
bool run(MachineFunction &MF);
60+
};
5161

62+
class SIPreAllocateWWMRegsLegacy : public MachineFunctionPass {
5263
public:
5364
static char ID;
5465

55-
SIPreAllocateWWMRegs() : MachineFunctionPass(ID) {
56-
initializeSIPreAllocateWWMRegsPass(*PassRegistry::getPassRegistry());
57-
}
66+
SIPreAllocateWWMRegsLegacy() : MachineFunctionPass(ID) {}
5867

5968
bool runOnMachineFunction(MachineFunction &MF) override;
6069

@@ -65,28 +74,24 @@ class SIPreAllocateWWMRegs : public MachineFunctionPass {
6574
AU.setPreservesAll();
6675
MachineFunctionPass::getAnalysisUsage(AU);
6776
}
68-
69-
private:
70-
bool processDef(MachineOperand &MO);
71-
void rewriteRegs(MachineFunction &MF);
7277
};
7378

7479
} // End anonymous namespace.
7580

76-
INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE,
77-
"SI Pre-allocate WWM Registers", false, false)
81+
INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE,
82+
"SI Pre-allocate WWM Registers", false, false)
7883
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
7984
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperPass)
8085
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperPass)
81-
INITIALIZE_PASS_END(SIPreAllocateWWMRegs, DEBUG_TYPE,
82-
"SI Pre-allocate WWM Registers", false, false)
86+
INITIALIZE_PASS_END(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE,
87+
"SI Pre-allocate WWM Registers", false, false)
8388

84-
char SIPreAllocateWWMRegs::ID = 0;
89+
char SIPreAllocateWWMRegsLegacy::ID = 0;
8590

86-
char &llvm::SIPreAllocateWWMRegsID = SIPreAllocateWWMRegs::ID;
91+
char &llvm::SIPreAllocateWWMRegsLegacyID = SIPreAllocateWWMRegsLegacy::ID;
8792

88-
FunctionPass *llvm::createSIPreAllocateWWMRegsPass() {
89-
return new SIPreAllocateWWMRegs();
93+
FunctionPass *llvm::createSIPreAllocateWWMRegsLegacyPass() {
94+
return new SIPreAllocateWWMRegsLegacy();
9095
}
9196

9297
bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {
@@ -184,7 +189,14 @@ SIPreAllocateWWMRegs::printWWMInfo(const MachineInstr &MI) {
184189

185190
#endif
186191

187-
bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
192+
bool SIPreAllocateWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {
193+
auto *LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
194+
auto *Matrix = &getAnalysis<LiveRegMatrixWrapperPass>().getLRM();
195+
auto *VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
196+
return SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);
197+
}
198+
199+
bool SIPreAllocateWWMRegs::run(MachineFunction &MF) {
188200
LLVM_DEBUG(dbgs() << "SIPreAllocateWWMRegs: function " << MF.getName() << "\n");
189201

190202
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
@@ -193,10 +205,6 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
193205
TRI = &TII->getRegisterInfo();
194206
MRI = &MF.getRegInfo();
195207

196-
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
197-
Matrix = &getAnalysis<LiveRegMatrixWrapperPass>().getLRM();
198-
VRM = &getAnalysis<VirtRegMapWrapperPass>().getVRM();
199-
200208
RegClassInfo.runOnMachineFunction(MF);
201209

202210
bool PreallocateSGPRSpillVGPRs =
@@ -254,3 +262,13 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
254262
rewriteRegs(MF);
255263
return true;
256264
}
265+
266+
PreservedAnalyses
267+
SIPreAllocateWWMRegsPass::run(MachineFunction &MF,
268+
MachineFunctionAnalysisManager &MFAM) {
269+
auto *LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
270+
auto *Matrix = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
271+
auto *VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
272+
SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);
273+
return PreservedAnalyses::all();
274+
}

‎llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
//===--- SIPreAllocateWWMRegs.h -------------------------------------------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#ifndef LLVM_LIB_TARGET_AMDGPU_SIPREALLOCATEWWMREGS_H
10+
#define LLVM_LIB_TARGET_AMDGPU_SIPREALLOCATEWWMREGS_H
11+
12+
#include "llvm/CodeGen/MachinePassManager.h"
13+
14+
namespace llvm {
15+
16+
class SIPreAllocateWWMRegsPass
17+
: public PassInfoMixin<SIPreAllocateWWMRegsPass> {
18+
public:
19+
PreservedAnalyses run(MachineFunction &MF,
20+
MachineFunctionAnalysisManager &MFAM);
21+
22+
MachineFunctionProperties getRequiredProperties() {
23+
return MachineFunctionProperties().set(
24+
MachineFunctionProperties::Property::IsSSA);
25+
}
26+
};
27+
28+
} // namespace llvm
29+
30+
#endif // LLVM_LIB_TARGET_AMDGPU_SIPREALLOCATEWWMREGS_H

‎llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
3+
4+
---
5+
6+
name: pre_allocate_wwm_regs_strict
7+
tracksRegLiveness: true
8+
body: |
9+
bb.0:
10+
liveins: $sgpr1
11+
; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
12+
; CHECK: liveins: $sgpr1
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
15+
; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
16+
; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
17+
; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec
18+
; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
19+
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
20+
%0:vgpr_32 = IMPLICIT_DEF
21+
renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
22+
%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
23+
%25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12, 15, 0, implicit $exec
24+
$exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
25+
%2:vgpr_32 = COPY %0:vgpr_32
26+
...

‎llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
3+
# This
4+
---
5+
6+
name: pre_allocate_wwm_spill_to_vgpr
7+
tracksRegLiveness: true
8+
body: |
9+
bb.0:
10+
liveins: $sgpr1
11+
; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
12+
; CHECK: liveins: $sgpr1
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
15+
; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
16+
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
17+
%0:vgpr_32 = IMPLICIT_DEF
18+
%23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
19+
%2:vgpr_32 = COPY %0:vgpr_32
20+
...
21+

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