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[RISCV] Support fixed vector vp.reverse/splice with Zvfhmin/Zvfbfmin.
Fix the names of some tests I accidentally misspelled.
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4 files changed

+81
-4
lines changed

4 files changed

+81
-4
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -756,8 +756,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
756756
ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO,
757757
ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS,
758758
ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::VP_LRINT,
759-
ISD::VP_LLRINT, ISD::EXPERIMENTAL_VP_REVERSE,
760-
ISD::EXPERIMENTAL_VP_SPLICE, ISD::VP_REDUCE_FMINIMUM,
759+
ISD::VP_LLRINT, ISD::VP_REDUCE_FMINIMUM,
761760
ISD::VP_REDUCE_FMAXIMUM, ISD::EXPERIMENTAL_VP_SPLAT};
762761

763762
static const unsigned IntegerVecReduceOps[] = {
@@ -1112,6 +1111,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
11121111
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
11131112

11141113
setOperationAction({ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE}, VT, Custom);
1114+
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
1115+
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
11151116

11161117
setOperationAction(FloatingPointVPOps, VT, Custom);
11171118

@@ -1418,6 +1419,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
14181419
ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_REVERSE,
14191420
ISD::VECTOR_SHUFFLE, ISD::VECTOR_COMPRESS},
14201421
VT, Custom);
1422+
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
1423+
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
14211424

14221425
setOperationAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
14231426
VT, Custom);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverser-float.ll renamed to llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-float.ll

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh -verify-machineinstrs -riscv-v-vector-bits-min=128 \
2+
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \
3+
; RUN: < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \
35
; RUN: < %s | FileCheck %s
46

57
define <2 x double> @test_vp_reverse_v2f64_masked(<2 x double> %src, <2 x i1> %mask, i32 zeroext %evl) {
@@ -88,3 +90,32 @@ define <4 x half> @test_vp_reverse_v4f16(<4 x half> %src, i32 zeroext %evl) {
8890
%dst = call <4 x half> @llvm.experimental.vp.reverse.v4f16(<4 x half> %src, <4 x i1> splat (i1 1), i32 %evl)
8991
ret <4 x half> %dst
9092
}
93+
94+
define <4 x bfloat> @test_vp_reverse_v4bf16_masked(<4 x bfloat> %src, <4 x i1> %mask, i32 zeroext %evl) {
95+
; CHECK-LABEL: test_vp_reverse_v4bf16_masked:
96+
; CHECK: # %bb.0:
97+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
98+
; CHECK-NEXT: vid.v v9, v0.t
99+
; CHECK-NEXT: addi a0, a0, -1
100+
; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t
101+
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
102+
; CHECK-NEXT: vmv1r.v v8, v9
103+
; CHECK-NEXT: ret
104+
%dst = call <4 x bfloat> @llvm.experimental.vp.reverse.v4bf16(<4 x bfloat> %src, <4 x i1> %mask, i32 %evl)
105+
ret <4 x bfloat> %dst
106+
}
107+
108+
define <4 x bfloat> @test_vp_reverse_v4bf16(<4 x bfloat> %src, i32 zeroext %evl) {
109+
; CHECK-LABEL: test_vp_reverse_v4bf16:
110+
; CHECK: # %bb.0:
111+
; CHECK-NEXT: addi a1, a0, -1
112+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
113+
; CHECK-NEXT: vid.v v9
114+
; CHECK-NEXT: vrsub.vx v10, v9, a1
115+
; CHECK-NEXT: vrgather.vv v9, v8, v10
116+
; CHECK-NEXT: vmv1r.v v8, v9
117+
; CHECK-NEXT: ret
118+
119+
%dst = call <4 x bfloat> @llvm.experimental.vp.reverse.v4bf16(<4 x bfloat> %src, <4 x i1> splat (i1 1), i32 %evl)
120+
ret <4 x bfloat> %dst
121+
}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverser-int.ll renamed to llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll‎

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfh -verify-machineinstrs -riscv-v-vector-bits-min=128 \
2+
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfh,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \
3+
; RUN: < %s | FileCheck %s
4+
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \
35
; RUN: < %s | FileCheck %s
46

57
define <2 x i64> @test_vp_splice_v2i64(<2 x i64> %va, <2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
@@ -299,3 +301,44 @@ define <8 x half> @test_vp_splice_v8f16_masked(<8 x half> %va, <8 x half> %vb, <
299301
%v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
300302
ret <8 x half> %v
301303
}
304+
305+
define <8 x bfloat> @test_vp_splice_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
306+
; CHECK-LABEL: test_vp_splice_v8bf16:
307+
; CHECK: # %bb.0:
308+
; CHECK-NEXT: addi a0, a0, -5
309+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
310+
; CHECK-NEXT: vslidedown.vi v8, v8, 5
311+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
312+
; CHECK-NEXT: vslideup.vx v8, v9, a0
313+
; CHECK-NEXT: ret
314+
315+
%v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
316+
ret <8 x bfloat> %v
317+
}
318+
319+
define <8 x bfloat> @test_vp_splice_v8bf16_negative_offset(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
320+
; CHECK-LABEL: test_vp_splice_v8bf16_negative_offset:
321+
; CHECK: # %bb.0:
322+
; CHECK-NEXT: addi a0, a0, -5
323+
; CHECK-NEXT: vsetivli zero, 5, e16, m1, ta, ma
324+
; CHECK-NEXT: vslidedown.vx v8, v8, a0
325+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
326+
; CHECK-NEXT: vslideup.vi v8, v9, 5
327+
; CHECK-NEXT: ret
328+
329+
%v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
330+
ret <8 x bfloat> %v
331+
}
332+
333+
define <8 x bfloat> @test_vp_splice_v8bf16_masked(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
334+
; CHECK-LABEL: test_vp_splice_v8bf16_masked:
335+
; CHECK: # %bb.0:
336+
; CHECK-NEXT: addi a0, a0, -5
337+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
338+
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
339+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
340+
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
341+
; CHECK-NEXT: ret
342+
%v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
343+
ret <8 x bfloat> %v
344+
}

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