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104 | 104 | #include "llvm/Transforms/Scalar/InferAddressSpaces.h" |
105 | 105 | #include "llvm/Transforms/Scalar/LoopDataPrefetch.h" |
106 | 106 | #include "llvm/Transforms/Scalar/NaryReassociate.h" |
| 107 | +#include "llvm/Transforms/Scalar/PackedIntegerCombinePass.h" |
107 | 108 | #include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h" |
108 | 109 | #include "llvm/Transforms/Scalar/Sink.h" |
109 | 110 | #include "llvm/Transforms/Scalar/StraightLineStrengthReduce.h" |
@@ -1378,8 +1379,11 @@ void AMDGPUPassConfig::addCodeGenPrepare() { |
1378 | 1379 |
|
1379 | 1380 | TargetPassConfig::addCodeGenPrepare(); |
1380 | 1381 |
|
1381 | | - if (isPassEnabled(EnableLoadStoreVectorizer)) |
| 1382 | + if (isPassEnabled(EnableLoadStoreVectorizer)) { |
1382 | 1383 | addPass(createLoadStoreVectorizerPass()); |
| 1384 | + // LSV pass opens up more opportunities for packed integer combining. |
| 1385 | + addPass(createPackedIntegerCombinePass()); |
| 1386 | + } |
1383 | 1387 |
|
1384 | 1388 | // LowerSwitch pass may introduce unreachable blocks that can |
1385 | 1389 | // cause unexpected behavior for subsequent passes. Placing it |
@@ -2101,8 +2105,11 @@ void AMDGPUCodeGenPassBuilder::addCodeGenPrepare(AddIRPass &addPass) const { |
2101 | 2105 |
|
2102 | 2106 | Base::addCodeGenPrepare(addPass); |
2103 | 2107 |
|
2104 | | - if (isPassEnabled(EnableLoadStoreVectorizer)) |
| 2108 | + if (isPassEnabled(EnableLoadStoreVectorizer)) { |
2105 | 2109 | addPass(LoadStoreVectorizerPass()); |
| 2110 | + // LSV pass opens up more opportunities for packed integer combining. |
| 2111 | + addPass(PackedIntegerCombinePass()); |
| 2112 | + } |
2106 | 2113 |
|
2107 | 2114 | // LowerSwitch pass may introduce unreachable blocks that can cause unexpected |
2108 | 2115 | // behavior for subsequent passes. Placing it here seems better that these |
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