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1 | | -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix CHK %s |
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
2 | 2 | ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s |
3 | 3 |
|
4 | | -; CHK-NOT: InlineAsm |
5 | | - |
6 | | -; CHECK-LABEL: foo: |
7 | | -; CHECK: bswapq |
8 | 4 | define i64 @foo(i64 %x) nounwind { |
| 5 | +; CHECK-LABEL: foo: |
| 6 | +; CHECK: ## %bb.0: |
| 7 | +; CHECK-NEXT: movq %rdi, %rax |
| 8 | +; CHECK-NEXT: bswapq %rax |
| 9 | +; CHECK-NEXT: retq |
9 | 10 | %asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind |
10 | 11 | ret i64 %asmtmp |
11 | 12 | } |
12 | 13 |
|
13 | | -; CHECK-LABEL: bar: |
14 | | -; CHECK: bswapq |
15 | 14 | define i64 @bar(i64 %x) nounwind { |
| 15 | +; CHECK-LABEL: bar: |
| 16 | +; CHECK: ## %bb.0: |
| 17 | +; CHECK-NEXT: movq %rdi, %rax |
| 18 | +; CHECK-NEXT: bswapq %rax |
| 19 | +; CHECK-NEXT: retq |
16 | 20 | %asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind |
17 | 21 | ret i64 %asmtmp |
18 | 22 | } |
19 | 23 |
|
20 | | -; CHECK-LABEL: pen: |
21 | | -; CHECK: bswapl |
22 | 24 | define i32 @pen(i32 %x) nounwind { |
| 25 | +; CHECK-LABEL: pen: |
| 26 | +; CHECK: ## %bb.0: |
| 27 | +; CHECK-NEXT: movl %edi, %eax |
| 28 | +; CHECK-NEXT: bswapl %eax |
| 29 | +; CHECK-NEXT: retq |
23 | 30 | %asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind |
24 | 31 | ret i32 %asmtmp |
25 | 32 | } |
26 | 33 |
|
27 | | -; CHECK-LABEL: s16: |
28 | | -; CHECK: rolw $8, |
29 | 34 | define zeroext i16 @s16(i16 zeroext %x) nounwind { |
| 35 | +; CHECK-LABEL: s16: |
| 36 | +; CHECK: ## %bb.0: |
| 37 | +; CHECK-NEXT: rolw $8, %di |
| 38 | +; CHECK-NEXT: movzwl %di, %eax |
| 39 | +; CHECK-NEXT: retq |
30 | 40 | %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind |
31 | 41 | ret i16 %asmtmp |
32 | 42 | } |
33 | 43 |
|
34 | | -; CHECK-LABEL: t16: |
35 | | -; CHECK: rolw $8, |
36 | 44 | define zeroext i16 @t16(i16 zeroext %x) nounwind { |
| 45 | +; CHECK-LABEL: t16: |
| 46 | +; CHECK: ## %bb.0: |
| 47 | +; CHECK-NEXT: rolw $8, %di |
| 48 | +; CHECK-NEXT: movzwl %di, %eax |
| 49 | +; CHECK-NEXT: retq |
37 | 50 | %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind |
38 | 51 | ret i16 %asmtmp |
39 | 52 | } |
40 | 53 |
|
41 | | -; CHECK-LABEL: u16: |
42 | | -; CHECK: rolw $8, |
43 | 54 | define zeroext i16 @u16(i16 zeroext %x) nounwind { |
| 55 | +; CHECK-LABEL: u16: |
| 56 | +; CHECK: ## %bb.0: |
| 57 | +; CHECK-NEXT: rolw $8, %di |
| 58 | +; CHECK-NEXT: movzwl %di, %eax |
| 59 | +; CHECK-NEXT: retq |
44 | 60 | %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind |
45 | 61 | ret i16 %asmtmp |
46 | 62 | } |
47 | 63 |
|
48 | | -; CHECK-LABEL: v16: |
49 | | -; CHECK: rolw $8, |
50 | 64 | define zeroext i16 @v16(i16 zeroext %x) nounwind { |
| 65 | +; CHECK-LABEL: v16: |
| 66 | +; CHECK: ## %bb.0: |
| 67 | +; CHECK-NEXT: rolw $8, %di |
| 68 | +; CHECK-NEXT: movzwl %di, %eax |
| 69 | +; CHECK-NEXT: retq |
51 | 70 | %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind |
52 | 71 | ret i16 %asmtmp |
53 | 72 | } |
54 | 73 |
|
55 | | -; CHECK-LABEL: s32: |
56 | | -; CHECK: bswapl |
57 | 74 | define i32 @s32(i32 %x) nounwind { |
| 75 | +; CHECK-LABEL: s32: |
| 76 | +; CHECK: ## %bb.0: |
| 77 | +; CHECK-NEXT: movl %edi, %eax |
| 78 | +; CHECK-NEXT: bswapl %eax |
| 79 | +; CHECK-NEXT: retq |
58 | 80 | %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind |
59 | 81 | ret i32 %asmtmp |
60 | 82 | } |
61 | 83 |
|
62 | | -; CHECK-LABEL: t32: |
63 | | -; CHECK: bswapl |
64 | 84 | define i32 @t32(i32 %x) nounwind { |
| 85 | +; CHECK-LABEL: t32: |
| 86 | +; CHECK: ## %bb.0: |
| 87 | +; CHECK-NEXT: movl %edi, %eax |
| 88 | +; CHECK-NEXT: bswapl %eax |
| 89 | +; CHECK-NEXT: retq |
65 | 90 | %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind |
66 | 91 | ret i32 %asmtmp |
67 | 92 | } |
68 | 93 |
|
69 | | -; CHECK-LABEL: u32: |
70 | | -; CHECK: bswapl |
71 | 94 | define i32 @u32(i32 %x) nounwind { |
| 95 | +; CHECK-LABEL: u32: |
| 96 | +; CHECK: ## %bb.0: |
| 97 | +; CHECK-NEXT: movl %edi, %eax |
| 98 | +; CHECK-NEXT: bswapl %eax |
| 99 | +; CHECK-NEXT: retq |
72 | 100 | %asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind |
73 | 101 | ret i32 %asmtmp |
74 | 102 | } |
75 | 103 |
|
76 | | -; CHECK-LABEL: s64: |
77 | | -; CHECK: bswapq |
78 | 104 | define i64 @s64(i64 %x) nounwind { |
| 105 | +; CHECK-LABEL: s64: |
| 106 | +; CHECK: ## %bb.0: |
| 107 | +; CHECK-NEXT: movq %rdi, %rax |
| 108 | +; CHECK-NEXT: bswapq %rax |
| 109 | +; CHECK-NEXT: retq |
79 | 110 | %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind |
80 | 111 | ret i64 %asmtmp |
81 | 112 | } |
82 | 113 |
|
83 | | -; CHECK-LABEL: t64: |
84 | | -; CHECK: bswapq |
85 | 114 | define i64 @t64(i64 %x) nounwind { |
| 115 | +; CHECK-LABEL: t64: |
| 116 | +; CHECK: ## %bb.0: |
| 117 | +; CHECK-NEXT: movq %rdi, %rax |
| 118 | +; CHECK-NEXT: bswapq %rax |
| 119 | +; CHECK-NEXT: retq |
86 | 120 | %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind |
87 | 121 | ret i64 %asmtmp |
88 | 122 | } |
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